diff -cNr yamon-sde6/arch/env/platform/env_platform.c yamon-devdrv/arch/env/platform/env_platform.c *** yamon-sde6/arch/env/platform/env_platform.c Wed Mar 24 01:50:28 2004 --- yamon-devdrv/arch/env/platform/env_platform.c Sat Jul 30 12:40:46 2005 *************** *** 96,101 **** --- 96,104 ---- ************************************************************************/ /* Default settings of env. variables */ + #ifdef _ARCH_DEVDRV_EKIT1100 + static char *default_ethaddr = "00.00.00.00.00.00"; + #endif static char *default_ip = "0.0.0.0"; static char *default_subnetmask; static char *default_gateway; *************** *** 254,259 **** --- 257,329 ---- switch( sys_platform ) { + #ifdef _ARCH_DEVDRV_EKIT1100 + case PRODUCT_THIRD_PARTY_ID: + + /* MAC address */ + if( default_switch || !env_get( "ethaddr", &raw, NULL, 0 ) ) + raw = default_ethaddr; /* Create new */ + if( env_set( "ethaddr", raw, ENV_ATTR_RW, + default_ethaddr, env_mac_s2num ) != OK ) + { + rc = FALSE; + } + + /* IP address */ + if( default_switch || !env_get( "ipaddr", &raw, NULL, 0 ) ) + raw = default_ip; /* Create new */ + if( env_set( "ipaddr", raw, ENV_ATTR_RW, + default_ip, ipaddr_ip_s2num ) != OK ) + { + rc = FALSE; + } + + /* Subnet mask */ + if( default_switch || !env_get( "subnetmask", &raw, NULL, 0 ) ) + raw = default_subnetmask; /* Create new */ + if( env_set( "subnetmask", raw, ENV_ATTR_RW, + default_subnetmask, subnetmask_ip_s2num ) != OK ) + { + rc = FALSE; + } + + /* Default gateway */ + if( default_switch || !env_get( "gateway", &raw, NULL, 0 ) ) + raw = default_gateway; /* Create new */ + if( env_set( "gateway", raw, ENV_ATTR_RW, + default_gateway, gateway_ip_s2num ) != OK ) + { + rc = FALSE; + } + + /* Default boot protocol */ + if( default_switch || !env_get( "bootprot", &raw, NULL, 0 ) ) + raw = default_bootprot; /* Create new */ + if( env_set( "bootprot", raw, ENV_ATTR_RW, + default_bootprot, env_decode_bootprot ) != OK ) + { + rc = FALSE; + } + + /* Default boot server (TFTP) */ + if( default_switch || !env_get( "bootserver", &raw, NULL, 0 ) ) + raw = default_bootserver; /* Create new */ + if( env_set( "bootserver", raw, ENV_ATTR_RW, + default_bootserver, env_ip_s2num ) != OK ) + { + rc = FALSE; + } + + /* Default boot file */ + if( default_switch || !env_get( "bootfile", &raw, NULL, 0 ) ) + raw = default_bootfile; /* Create new */ + if( env_set( "bootfile", raw, ENV_ATTR_RW, + default_bootfile, NULL ) != OK ) + { + rc = FALSE; + } + break; + #else case PRODUCT_MALTA_ID : case PRODUCT_ATLASA_ID : *************** *** 356,361 **** --- 426,432 ---- case PRODUCT_SEAD2_ID : break; + #endif /* #ifdef _ARCH_DEVDRV_EKIT1100 */ default : break; diff -cNr yamon-sde6/arch/exception/platform/excep_platform.c yamon-devdrv/arch/exception/platform/excep_platform.c *** yamon-sde6/arch/exception/platform/excep_platform.c Wed Mar 24 01:50:28 2004 --- yamon-devdrv/arch/exception/platform/excep_platform.c Wed Aug 3 13:58:51 2005 *************** *** 94,99 **** --- 94,104 ---- #include #include + /* E!Kit-1100 */ + #ifdef _ARCH_DEVDRV_EKIT1100 + #include + #endif + /************************************************************************ * Definitions ************************************************************************/ *************** *** 152,157 **** --- 157,168 ---- switch( sys_platform ) { + #ifdef _ARCH_DEVDRV_EKIT1100 + case PRODUCT_THIRD_PARTY_ID: + *ic_count = 32; + *ic_int = C0_STATUS_IM_HW0; + break; + #else case PRODUCT_ATLASA_ID : /* Atlas interrupt controller (icta) needs no initialisation */ *************** *** 307,312 **** --- 318,324 ---- break; } /* else fall through */ + #endif /* #ifdef _ARCH_DEVDRV_EKIT1100 */ default : *************** *** 338,343 **** --- 350,369 ---- { switch( sys_platform ) { + #ifdef _ARCH_DEVDRV_EKIT1100 + case PRODUCT_THIRD_PARTY_ID: + /* High Level Enabled */ + REG(KSEG1(AU1X00_IC0_BASE), AU1X00_IC_CFG0SET) = 1 << ic_line; + REG(KSEG1(AU1X00_IC0_BASE), AU1X00_IC_CFG1CLR) = 1 << ic_line; + REG(KSEG1(AU1X00_IC0_BASE), AU1X00_IC_CFG2SET) = 1 << ic_line; + /* Peripheral interrupt */ + REG(KSEG1(AU1X00_IC0_BASE), AU1X00_IC_SRCSET) = 1 << ic_line; + /* Assign interrupt to request 0 */ + REG(KSEG1(AU1X00_IC0_BASE), AU1X00_IC_ASSIGNSET) = 1 << ic_line; + /* Enable the interrupt */ + REG(KSEG1(AU1X00_IC0_BASE), AU1X00_IC_MASKSET) = 1 << ic_line; + break; + #else case PRODUCT_ATLASA_ID : REG32(KSEG1( ATLAS_ICTA_BASE + ICTA_INTSETEN_OFS )) = *************** *** 359,364 **** --- 385,391 ---- } break; + #endif /* #ifdef _ARCH_DEVDRV_EKIT1100 */ default : *************** *** 388,393 **** --- 415,428 ---- { switch( sys_platform ) { + #ifdef _ARCH_DEVDRV_EKIT1100 + case PRODUCT_THIRD_PARTY_ID: + /* Interrupts Disabled */ + REG(KSEG1(AU1X00_IC0_BASE), AU1X00_IC_CFG0CLR) = 1 << ic_line; + REG(KSEG1(AU1X00_IC0_BASE), AU1X00_IC_CFG1CLR) = 1 << ic_line; + REG(KSEG1(AU1X00_IC0_BASE), AU1X00_IC_CFG2CLR) = 1 << ic_line; + break; + #else case PRODUCT_ATLASA_ID : REG32(KSEG1( ATLAS_ICTA_BASE + ICTA_INTRSTEN_OFS )) = *************** *** 406,411 **** --- 441,447 ---- } break; + #endif /* #ifdef _ARCH_DEVDRV_EKIT1100 */ default : *************** *** 438,443 **** --- 474,484 ---- switch( sys_platform ) { + #ifdef _ARCH_DEVDRV_EKIT1100 + case PRODUCT_THIRD_PARTY_ID: + /* Shows active interrupts on request 0 */ + return REG(KSEG1(AU1X00_IC0_BASE), AU1X00_IC_REQ0INT); + #else case PRODUCT_ATLASA_ID : /* Return all pending interrupts */ *************** *** 485,490 **** --- 526,532 ---- /* Return all pending interrupts */ return REG(MSC01_IC_REG_BASE, MSC01_IC_ISAL); + #endif /* #ifdef _ARCH_DEVDRV_EKIT1100 */ default : /* No interrupt controller */ diff -cNr yamon-sde6/arch/freq/platform/freq_platform.c yamon-devdrv/arch/freq/platform/freq_platform.c *** yamon-sde6/arch/freq/platform/freq_platform.c Wed Mar 24 01:50:28 2004 --- yamon-devdrv/arch/freq/platform/freq_platform.c Wed Aug 3 13:53:47 2005 *************** *** 83,88 **** --- 83,91 ---- #include #include #include + #ifdef _ARCH_DEVDRV_EKIT1100 + #include + #endif /************************************************************************ * Definitions *************** *** 276,281 **** --- 279,293 ---- switch( sys_platform ) { + #ifdef _ARCH_DEVDRV_EKIT1100 + case PRODUCT_THIRD_PARTY_ID: + /* Estimate cpu clock frequency */ + sys_cpufreq_hz = (REG(KSEG1(AU1X00_SYS_BASE), AU1X00_SYS_CPUPLL) & 0x3F) * EKIT1100_CPUOSC_FREQ; + /* Estimate bus clock frequency */ + DISP_STR("FREQBUS"); + sys_busfreq_hz = sys_cpufreq_hz / ((REG(KSEG1(AU1X00_SYS_BASE), AU1X00_SYS_POWERCTRL) & 0x03) + 2); + break; + #else case PRODUCT_ATLASA_ID : case PRODUCT_MALTA_ID : *************** *** 299,304 **** --- 311,317 ---- sys_busfreq_hz = sys_cpufreq_hz; break; + #endif /* #ifdef _ARCH_DEVDRV_EKIT1100 */ default : /* Should never happen */ break; } diff -cNr yamon-sde6/arch/include/ekit1100.h yamon-devdrv/arch/include/ekit1100.h *** yamon-sde6/arch/include/ekit1100.h Thu Jan 1 09:00:00 1970 --- yamon-devdrv/arch/include/ekit1100.h Thu Aug 4 11:30:20 2005 *************** *** 0 **** --- 1,205 ---- + + /************************************************************************ + * + * ekit1100.h + * + * The 'ekit1100' module defines the E!Kit-1100 board specific + * address-MAP, registers, etc. + * + * ###################################################################### + * + * This file is largely copies by the other boards source files. + * + * Copyright 2005 Device Drivers Limited. + * Author: kawamoto@devdrv.co.jp + * + ************************************************************************/ + + #ifndef EKIT1100_H + #define EKIT1100_H + + /************************************************************************ + * Note: all addresses are physical ! + * Must be mapped into kseg0 (system RAM) or kseg1 (registers, devices) + *************************************************************************/ + + /************************************************************************ + * E!Kit-1100 physical address MAP (512 MByte) + *************************************************************************/ + + #define EKIT1100_SYSTEMRAM_BASE 0x00000000 /* System RAM: */ + #define EKIT1100_SYSTEMRAM_SIZE 0x08000000 /* 128 MByte */ + + #define EKIT1100_SYSTEMFLASH_BASE 0x1F800000 /* System Flash: */ + #define EKIT1100_SYSTEMFLASH_SIZE 0x00400000 /* 4 MByte */ + + #define EKIT1100_SYSTEMFLASH_SECTORSIZE 0x00010000 /* Sect. = 64 KB */ + #define EKIT1100_SYSTEMFLASH_BANKCOUNT 1 /* */ + #define EKIT1100_SYSTEMFLASH_BLOCKCOUNT 63 /* */ + + #define EKIT1100_MONITORFLASH_BASE 0x1FC00000 /* Monitor Flash: */ + #define EKIT1100_MONITORFLASH_SIZE 0x003C0000 /* 3.75 MByte */ + #define EKIT1100_MONITORFLASH_SECTORSIZE 0x00010000 /* Sect. = 64 KB */ + + #define EKIT1100_FILEFLASH_BASE 0x1FFC0000 /* File Flash: */ + #define EKIT1100_FILEFLASH_SIZE 0x00040000 /* 256 KByte */ + #define EKIT1100_FILEFLASH_SECTORSIZE 0x00010000 /* Sect. = 64 KB */ + + /************************************************************************ + * BCSR physical address MAP + ************************************************************************/ + + #define EKIT1100_BCSR_BASE 0x18000000 /* FPGA: */ + #define EKIT1100_BCSR_SIZE 0x02000000 /* 32 MByte */ + + #define EKIT1100_BCSR_CF0_OFS 0x0000 + #define EKIT1100_BCSR_CF1_OFS 0x0004 + #define EKIT1100_BCSR_USB0_OFS 0x0008 + #define EKIT1100_BCSR_USB1_OFS 0x000C + #define EKIT1100_BCSR_SYS_OFS 0x0010 + #define EKIT1100_BCSR_GPIO3_OFS 0x0014 + #define EKIT1100_BCSR_CONFIG_OFS 0x001C + + /************************************************************************ + * Au1X00 Processor physical address MAP + *************************************************************************/ + + /* SDRAM Memory Controller */ + #define AU1X00_MEM_BASE 0x14000000 + + #define AU1X00_MEM_SDMODE0_OFS 0x0000 + #define AU1X00_MEM_SDMODE1_OFS 0x0004 + #define AU1X00_MEM_SDMODE2_OFS 0x0008 + #define AU1X00_MEM_SDADDR0_OFS 0x000C + #define AU1X00_MEM_SDADDR1_OFS 0x0010 + #define AU1X00_MEM_SDADDR2_OFS 0x0014 + #define AU1X00_MEM_SDREFCFG_OFS 0x0018 + #define AU1X00_MEM_SDPRECMD_OFS 0x001C + #define AU1X00_MEM_SDAUTOREF_OFS 0x0020 + #define AU1X00_MEM_SDWRMD0_OFS 0x0024 + #define AU1X00_MEM_SDWRMD1_OFS 0x0028 + #define AU1X00_MEM_SDWRMD2_OFS 0x002C + #define AU1X00_MEM_SDSLEEP_OFS 0x0030 + #define AU1X00_MEM_SDSMCKE_OFS 0x0034 + + #define AU1X00_MEM_STCFG0_OFS 0x1000 + #define AU1X00_MEM_STTIME0_OFS 0x1004 + #define AU1X00_MEM_STADDR0_OFS 0x1008 + #define AU1X00_MEM_STCFG1_OFS 0x1010 + #define AU1X00_MEM_STTIME1_OFS 0x1014 + #define AU1X00_MEM_STADDR1_OFS 0x1018 + #define AU1X00_MEM_STCFG2_OFS 0x1020 + #define AU1X00_MEM_STTIME2_OFS 0x1024 + #define AU1X00_MEM_STADDR2_OFS 0x1028 + #define AU1X00_MEM_STCFG3_OFS 0x1030 + #define AU1X00_MEM_STTIME3_OFS 0x1034 + #define AU1X00_MEM_STADDR3_OFS 0x1038 + + /* Interrupt Controller */ + #define AU1X00_IC0_BASE 0x10400000 + #define AU1X00_IC1_BASE 0x11800000 + + #define AU1X00_IC_CFG0RD_OFS 0x0040 + #define AU1X00_IC_CFG0SET_OFS 0x0040 + #define AU1X00_IC_CFG0CLR_OFS 0x0044 + #define AU1X00_IC_CFG1RD_OFS 0x0048 + #define AU1X00_IC_CFG1SET_OFS 0x0048 + #define AU1X00_IC_CFG1CLR_OFS 0x004C + #define AU1X00_IC_CFG2RD_OFS 0x0050 + #define AU1X00_IC_CFG2SET_OFS 0x0050 + #define AU1X00_IC_CFG2CLR_OFS 0x0054 + #define AU1X00_IC_REQ0INT_OFS 0x0054 + #define AU1X00_IC_SRCRD_OFS 0x0058 + #define AU1X00_IC_SRCSET_OFS 0x0058 + #define AU1X00_IC_SRCCLR_OFS 0x005C + #define AU1X00_IC_REQ1INT_OFS 0x005C + #define AU1X00_IC_ASSIGNRD_OFS 0x0060 + #define AU1X00_IC_ASSIGNSET_OFS 0x0060 + #define AU1X00_IC_ASSIGNCLR_OFS 0x0064 + #define AU1X00_IC_WAKERD_OFS 0x0068 + #define AU1X00_IC_WAKESET_OFS 0x006C + #define AU1X00_IC_WAKECLR_OFS 0x0070 + #define AU1X00_IC_MASKRD_OFS 0x0070 + #define AU1X00_IC_MASKSET_OFS 0x0074 + #define AU1X00_IC_MASKCLR_OFS 0x0078 + #define AU1X00_IC_RISINGRD_OFS 0x0078 + #define AU1X00_IC_RISINGCLR_OFS 0x007C + #define AU1X00_IC_FALLINGRD_OFS 0x007C + #define AU1X00_IC_FALLINGCLR_OFS 0x0080 + + /* UART Interfaces */ + #define AU1X00_UART0_BASE 0x11100000 + #define AU1X00_UART1_BASE 0x11200000 + #define AU1X00_UART3_BASE 0x11400000 + + #define AU1X00_UART_RXDATA_OFS 0x0000 + #define AU1X00_UART_TXDATA_OFS 0x0004 + #define AU1X00_UART_INTEN_OFS 0x0008 + #define AU1X00_UART_INTCAUSE_OFS 0x000C + #define AU1X00_UART_FIFOCTRL_OFS 0x0010 + #define AU1X00_UART_LINECTRL_OFS 0x0014 + #define AU1X00_UART_MDMCTRL_OFS 0x0018 + #define AU1X00_UART_LINESTAT_OFS 0x001C + #define AU1X00_UART_MDMSTAT_OFS 0x0020 + #define AU1X00_UART_AUTOFLOW_OFS 0x0024 + #define AU1X00_UART_CLKDIV_OFS 0x0028 + #define AU1X00_UART_ENABLE_OFS 0x0100 + + /* System Control Block Base Address */ + #define AU1X00_SYS_BASE 0x11900000 + + /* Time of Year Clock and Real Time Clock */ + #define AU1X00_SYS_TOYTRIM_OFS 0x0000 + #define AU1X00_SYS_TOYWRITE_OFS 0x0004 + #define AU1X00_SYS_TOYMATCH0_OFS 0x0008 + #define AU1X00_SYS_TOYMATCH1_OFS 0x000C + #define AU1X00_SYS_TOYMATCH2_OFS 0x0010 + #define AU1X00_SYS_CNTRCTRL_OFS 0x0014 + #define AU1X00_SYS_TOYREAD_OFS 0x0040 + #define AU1X00_SYS_RTCTRIM_OFS 0x0044 + #define AU1X00_SYS_RTCWRITE_OFS 0x0048 + #define AU1X00_SYS_RTCMATCH0_OFS 0x004C + #define AU1X00_SYS_RTCMATCH1_OFS 0x0050 + #define AU1X00_SYS_RTCMATCH2_OFS 0x0054 + #define AU1X00_SYS_RTCREAD_OFS 0x0058 + + /* Primary GPIO */ + #define AU1X00_SYS_PINFUNC_OFS 0x002C + + /* Power Management */ + #define AU1X00_SYS_ENDIAN_OFS 0x0038 + #define AU1X00_SYS_POWERCTRL_OFS 0x003C + + /* Clock Controller */ + #define AU1X00_SYS_FREQCTRL0_OFS 0x0020 + #define AU1X00_SYS_FREQCTRL1_OFS 0x0024 + #define AU1X00_SYS_CLKSRC_OFS 0x0028 + #define AU1X00_SYS_CPUPLL_OFS 0x0060 + #define AU1X00_SYS_AUXPLL_OFS 0x0064 + + /********************************************************************/ + + #define EKIT1100_CPUOSC_FREQ 12000000 /* 12MHz */ + #define EKIT1100_SYS_CPUPLL 33 /* 396MHz */ + #define EKIT1100_SYS_POWERCTRL 0 /* SD=2 */ + #define EKIT1100_SYS_AUXPLL 8 /* 96MHz */ + + #define AU1X00_UART0_INT 0 + #define AU1X00_UART1_INT 1 + #define AU1X00_UART3_INT 3 + #define AU1X00_MAC0_DMA_INT 28 + + #define EKIT1100_MEM_STCFG0 0x00060043 + #define EKIT1100_MEM_STTIME0 0x040181D7 + #define EKIT1100_MEM_STADDR0 0x11F83FE0 + #define EKIT1100_MEM_STCFG1 0x000000C0 + #define EKIT1100_MEM_STTIME1 0x22080A20 + #define EKIT1100_MEM_STADDR1 0x11803F80 + #define EKIT1100_MEM_STCFG2 0x000000C0 + #define EKIT1100_MEM_STTIME2 0x22080A20 + #define EKIT1100_MEM_STADDR2 0x11A03F80 + #define EKIT1100_MEM_STCFG3 0x00000002 + #define EKIT1100_MEM_STTIME3 0x280E3E07 + #define EKIT1100_MEM_STADDR3 0x10000000 + + #endif /* #ifndef EKIT1100_H */ diff -cNr yamon-sde6/arch/include/initswitch.h yamon-devdrv/arch/include/initswitch.h *** yamon-sde6/arch/include/initswitch.h Wed Mar 24 01:50:28 2004 --- yamon-devdrv/arch/include/initswitch.h Mon Sep 26 17:39:10 2005 *************** *** 99,104 **** --- 99,117 ---- * *********************************************************************/ + #ifdef _ARCH_DEVDRV_EKIT1100 + #define INCLUDE_SYSCON 1 + #define INCLUDE_IO 1 + #define INCLUDE_EXCEP 1 + #define INCLUDE_RTC_AU1X00 1 + #define INCLUDE_FREQ 1 + #define INCLUDE_FLASH_AMD 1 + #define INCLUDE_SYSENV 1 + #define INCLUDE_ENV 1 + #define INCLUDE_SERIAL_AU1X00 1 + #define INCLUDE_LAN_AU1X00 1 + #define INCLUDE_NET 1 + #else #define INCLUDE_SYSCON 1 #define INCLUDE_IO 1 #define INCLUDE_EXCEP 1 *************** *** 115,119 **** --- 128,133 ---- #define INCLUDE_LAN_AM79C973 1 #define INCLUDE_NET 1 #define INCLUDE_IDE 1 + #endif /* #ifdef _ARCH_DEVDRV_EKIT1100 */ diff -cNr yamon-sde6/arch/include/mips.h yamon-devdrv/arch/include/mips.h *** yamon-sde6/arch/include/mips.h Wed Mar 24 01:50:28 2004 --- yamon-devdrv/arch/include/mips.h Thu Aug 4 14:18:39 2005 *************** *** 217,222 **** --- 217,228 ---- #define QED_RM70XX ( (C0_PRID_COMP_NOT_MIPS32_64 << \ S_PRIdCoID) | \ (C0_PRID_PRID_RM70XX << S_PRIdImp) ) + #ifdef _ARCH_DEVDRV_EKIT1100 + #define ALCHEMY_REV1 ( (K_PRIdCoID_Alchemy << S_PRIdCoID) | \ + (1 << S_PRIdImp) ) + #define ALCHEMY_REV2 ( (K_PRIdCoID_Alchemy << S_PRIdCoID) | \ + (2 << S_PRIdImp) ) + #endif /* cache operations */ diff -cNr yamon-sde6/arch/include/syscon.h yamon-devdrv/arch/include/syscon.h *** yamon-sde6/arch/include/syscon.h Wed Mar 24 01:50:28 2004 --- yamon-devdrv/arch/include/syscon.h Fri Jul 22 19:36:53 2005 *************** *** 262,267 **** --- 262,274 ---- void syscon_register_id_board( t_syscon_ids id, /* OBJECT ID from syscon_api.h */ + #ifdef _ARCH_DEVDRV_EKIT1100 + /* E!Kit-1100 */ + t_syscon_func read_ekit1, /* E!Kit-1100 read function */ + void *read_data_ekit1, /* Registered data */ + t_syscon_func write_ekit1, /* E!Kit-1100 write function */ + void *write_data_ekit1 ); /* Registered data */ + #else /* Atlas */ t_syscon_func read_atlas, /* Atlas read function */ void *read_data_atlas, /* Registered data */ *************** *** 277,282 **** --- 284,290 ---- void *read_data_malta, /* Registered data */ t_syscon_func write_malta, /* Malta write function */ void *write_data_malta ); /* Registered data */ + #endif /* #ifdef _ARCH_DEVDRV_EKIT1100 */ /************************************************************************ *************** *** 303,308 **** --- 311,323 ---- void syscon_register_id_core( t_syscon_ids id, /* OBJECT ID from syscon_api.h */ + #ifdef _ARCH_DEVDRV_EKIT1100 + /* E!Kit-1100 */ + t_syscon_func read_ekit1, /* E!Kit-1100 read function */ + void *read_data_ekit1, /* Registered data */ + t_syscon_func write_ekit1, /* E!Kit-1100 write function */ + void *write_data_ekit1 ); /* Registered data */ + #else /* Galileo based */ t_syscon_func read_galileo, /* Core Galileo read function */ *************** *** 321,326 **** --- 336,342 ---- void *read_data_bonito64, /* Registered data */ t_syscon_func write_bonito64, /* Core Bonito64 write */ void *write_data_bonito64 ); /* Registered data */ + #endif /* #ifdef _ARCH_DEVDRV_EKIT1100 */ /************************************************************************ diff -cNr yamon-sde6/arch/init/platform/init_platform.c yamon-devdrv/arch/init/platform/init_platform.c *** yamon-sde6/arch/init/platform/init_platform.c Wed Mar 24 01:50:28 2004 --- yamon-devdrv/arch/init/platform/init_platform.c Tue Jul 26 00:08:39 2005 *************** *** 82,87 **** --- 82,90 ---- #include #include /* Malta specific */ #include /* Malta specific */ + #ifdef _ARCH_DEVDRV_EKIT1100 + #include + #endif /************************************************************************ * Definitions *************** *** 183,188 **** --- 186,195 ---- */ switch( sys_platform ) { + #ifdef _ARCH_DEVDRV_EKIT1100 + case PRODUCT_THIRD_PARTY_ID: + break; + #else case PRODUCT_SEAD2_ID : /* SEAD with SOC-it 101 shares a lot of code with coreSYS */ /* That is achieved by setting up an artificial core card */ *************** *** 412,417 **** --- 419,425 ---- arch_core_init( TRUE, ATLAS_INTLINE_COREHI, FALSE ); break; + #endif /* #ifdef _ARCH_DEVDRV_EKIT1100 */ default : *************** *** 424,429 **** --- 432,441 ---- switch( sys_platform ) { + #ifdef _ARCH_DEVDRV_EKIT1100 + case PRODUCT_THIRD_PARTY_ID: + break; + #else case PRODUCT_ATLASA_ID : /* Perform core specific initialisation */ *************** *** 482,487 **** --- 494,500 ---- PIIX4_GLBCTL_EOS_BIT ); break; + #endif /* #ifdef _ARCH_DEVDRV_EKIT1100 */ default : break; diff -cNr yamon-sde6/arch/init/platform/initmodules.c yamon-devdrv/arch/init/platform/initmodules.c *** yamon-sde6/arch/init/platform/initmodules.c Wed Mar 24 01:50:28 2004 --- yamon-devdrv/arch/init/platform/initmodules.c Mon Sep 26 10:27:42 2005 *************** *** 153,158 **** --- 153,167 ---- #endif + #if INCLUDE_RTC_AU1X00 /* Depends on IO */ + if (product == PRODUCT_THIRD_PARTY_ID) + { + DISP_STR( "RTC" ); + RTC_AU1X00_install(); + } + #endif + + #if INCLUDE_FREQ /* Depends on RTC */ DISP_STR( "FREQ" ); freq_init(); *************** *** 215,220 **** --- 224,235 ---- #endif + #if INCLUDE_FLASH_AMD /* Depends on IO */ + DISP_STR( "FLASH" ); + FLASH_AMD_install(); + #endif + + #if INCLUDE_SYSENV /* Depends on FLASH_STRATA */ DISP_STR( "SYSENV" ); SYSENV_init(); *************** *** 237,242 **** --- 252,263 ---- #endif + #if INCLUDE_SERIAL_AU1X00 /* Depends on ENV */ + DISP_STR( "SERIAL" ); + SERIAL_AU1X00_install(); + #endif + + #if INCLUDE_LAN_SAA9730 /* Depends on ENV */ if( product == PRODUCT_ATLASA_ID ) { *************** *** 255,260 **** --- 276,290 ---- #endif + #if INCLUDE_LAN_AU1X00 /* Depends on ENV */ + if (product == PRODUCT_THIRD_PARTY_ID) + { + DISP_STR( "AU1X00_LAN" ); + LAN_AU1X00_install(); + } + #endif + + #if INCLUDE_NET /* Depends on LAN driver */ DISP_STR( "NET" ); NET_init() ; diff -cNr yamon-sde6/arch/reset/bootvector/reset.S yamon-devdrv/arch/reset/bootvector/reset.S *** yamon-sde6/arch/reset/bootvector/reset.S Wed Mar 24 01:50:28 2004 --- yamon-devdrv/arch/reset/bootvector/reset.S Wed Aug 3 13:26:52 2005 *************** *** 75,80 **** --- 75,83 ---- #include #include #include + #ifdef _ARCH_DEVDRV_EKIT1100 + #include + #endif /************************************************************************ * Definitions *************** *** 129,137 **** --- 132,174 ---- nop /* 0xBfc00004 */ nop /* 0xBfc00008 */ nop /* 0xBfc0000C */ + #ifdef _ARCH_DEVDRV_EKIT1100 + .word 0x000000E0/* 0xBfc00010 - illegal board if not intercepted */ + .word 0x00000000/* 0xBfc00014 - expanded to 64 bit */ + 1: + /* Establish CPU endian mode. */ + li t0, KSEG1BASE + li t1, AU1X00_MEM_BASE + or t0, t0, t1 + li t1, EKIT1100_MEM_STCFG1 + sw t1, AU1X00_MEM_STCFG1_OFS(t0) + li t1, EKIT1100_MEM_STTIME1 + sw t1, AU1X00_MEM_STTIME1_OFS(t0) + li t1, EKIT1100_MEM_STADDR1 + sw t1, AU1X00_MEM_STADDR1_OFS(t0) + + li t0, KSEG1BASE + li t1, EKIT1100_BCSR_BASE + or t0, t0, t1 + lw t1, EKIT1100_BCSR_CONFIG_OFS(t0) + andi t1, t1, 1 + bne zero, t1, 1f + nop + + /* Change Au1 core to little endian */ + li t0, KSEG1BASE + li t1, AU1X00_SYS_BASE + or t0, t0, t1 + li t1, 1 + sw t1, AU1X00_SYS_ENDIAN_OFS(t0) + MFC0( t2, C0_Config) + MTC0( t2, C0_Config) + 1: + #else .word 0xffffffff/* 0xBfc00010 - illegal board if not intercepted */ .word 0xffffffff/* 0xBfc00014 - expanded to 64 bit */ 1: + #endif /* #ifdef _ARCH_DEVDRV_EKIT1100 */ /* Clear watch registers */ MTC0( zero, C0_WatchLo) MTC0( zero, C0_WatchHi) diff -cNr yamon-sde6/arch/reset/ekit1100_platform.S yamon-devdrv/arch/reset/ekit1100_platform.S *** yamon-sde6/arch/reset/ekit1100_platform.S Thu Jan 1 09:00:00 1970 --- yamon-devdrv/arch/reset/ekit1100_platform.S Tue Sep 27 14:15:47 2005 *************** *** 0 **** --- 1,779 ---- + + /************************************************************************ + * + * ekit1100_platform.S + * + * E!Kit-1100 specific initialisation + * + * ###################################################################### + * + * This file is largely copies by the other boards source files. + * + * Copyright 2005 Device Drivers Limited. + * Author: kawamoto@devdrv.co.jp + * + ************************************************************************/ + + /************************************************************************ + * Include files + ************************************************************************/ + + #include + #include + #include + #include + + /********************************************************************/ + + /* + * Au1100 base addresses (in KSEG1 region) + */ + #define AU1X00_MEM_ADDR 0xB4000000 + #define AU1X00_AC97_ADDR 0xB0000000 + #define AU1X00_USBH_ADDR 0xB0100000 + #define AU1X00_USBD_ADDR 0xB0200000 + #define AU1X00_IC0_ADDR 0xB0400000 + #define AU1X00_MACEN_ADDR 0xB0520000 + #define AU1X00_UART0_ADDR 0xB1100000 + #define AU1X00_UART3_ADDR 0xB1400000 + #define AU1X00_GPIO2_ADDR 0xB1700000 + #define AU1X00_IC1_ADDR 0xB1800000 + #define AU1X00_SYS_ADDR 0xB1900000 + #define AU1X00_LCD_ADDR 0xB5000000 + + /* + * Au1100 memory controller register offsets + */ + #define mem_sdmode0 0x0000 + #define mem_sdmode1 0x0004 + #define mem_sdmode2 0x0008 + #define mem_sdaddr0 0x000C + #define mem_sdaddr1 0x0010 + #define mem_sdaddr2 0x0014 + #define mem_sdrefcfg 0x0018 + #define mem_sdprecmd 0x001C + #define mem_sdautoref 0x0020 + #define mem_sdwrmd0 0x0024 + #define mem_sdwrmd1 0x0028 + #define mem_sdwrmd2 0x002C + #define mem_sdsleep 0x0030 + #define mem_sdsmcke 0x0034 + + #define mem_stcfg0 0x1000 + #define mem_sttime0 0x1004 + #define mem_staddr0 0x1008 + #define mem_stcfg1 0x1010 + #define mem_sttime1 0x1014 + #define mem_staddr1 0x1018 + #define mem_stcfg2 0x1020 + #define mem_sttime2 0x1024 + #define mem_staddr2 0x1028 + #define mem_stcfg3 0x1030 + #define mem_sttime3 0x1034 + #define mem_staddr3 0x1038 + + /* + * Au1100 peripheral register offsets + */ + #define ac97_enable 0x0010 + #define usbh_enable 0x0007FFFC + #define usbd_enable 0x0058 + #define irda_enable 0x0040 + #define macen_mac0 0x0000 + #define macen_mac1 0x0004 + #define i2s_enable 0x0008 + #define uart_enable 0x0100 + #define ssi_enable 0x0100 + #define lcd_control 0x0000 + + #define ic_cfg0clr 0x0044 + #define ic_cfg1clr 0x004C + #define ic_cfg2clr 0x0054 + #define ic_srcset 0x0058 + #define ic_assignset 0x0060 + #define ic_wakeclr 0x006C + #define ic_maskclr 0x0074 + #define ic_risingclr 0x0078 + #define ic_fallingclr 0x007C + #define ic_testbit 0x0080 + + #define sys_scratch0 0x0018 + #define sys_scratch1 0x001c + #define sys_cntctrl 0x0014 + #define sys_freqctrl0 0x0020 + #define sys_freqctrl1 0x0024 + #define sys_clksrc 0x0028 + #define sys_pinfunc 0x002C + #define sys_wakemsk 0x0034 + #define sys_powerctrl 0x003C + #define sys_endian 0x0038 + #define sys_wakesrc 0x005C + #define sys_cpupll 0x0060 + #define sys_auxpll 0x0064 + #define sys_trioutclr 0x0100 + #define sys_outputset 0x0108 + #define sys_outputclr 0x010C + #define sys_pininputen 0x0110 + + #define gpio2_dir 0x0000 + #define gpio2_output 0x0008 + #define gpio2_pinstate 0x000C + #define gpio2_inten 0x0010 + #define gpio2_enable 0x0014 + + /********************************************************************/ + + /* + * Aurum-specific values + * NOTE: All values are for operation at 396MHz, SD=2 + */ + + #define SYS_CPUPLL 33 /* 396MHz */ + #define SYS_POWERCTRL 0 /* SD=2 */ + #define SYS_AUXPLL 8 /* 96MHz */ + + /* RCE0: FUJITSU MBM29LV650UE-90TN Flash + * + * Field Flash - 120ns + * Ta tRC 120ns yields 24 clocks - 1 + * Tpm tPACC 40ns yields 8 clocks - 1 + * Tcsw tCS 0ns + * Twp tWP 35ns yields 7 clocks - 1 + * Tcsh MAX(tCH 0ns, tDF 25ns) yields 5 clocks - 1 + * Twcs tCH 0ns + */ + #define MEM_STCFG0 0x00060043 + #define MEM_STTIME0 0x040181D7 + #define MEM_STADDR0 0x11F83FE0 + + /* RCE1: CPLD Board Logic */ + #define MEM_STCFG1 0x000000C0 + #define MEM_STTIME1 0x22080A20 + #define MEM_STADDR1 0x11803F80 + + /* RCE2: */ + #define MEM_STCFG2 0x000000C0 + #define MEM_STTIME2 0x22080A20 + #define MEM_STADDR2 0x11A03F80 + + /* RCE3: PCMCIA 250ns */ + #define MEM_STCFG3 0x00000002 + #define MEM_STTIME3 0x280E3E07 + #define MEM_STADDR3 0x10000000 + + /* + * SDCS0 - 64MB K4S561632D-TC75 + * SDCS1 - 64MB K4S561632D-TC75 + * SDCS2 - None + */ + #define MEM_SDMODE0 0x005922A9 + #define MEM_SDMODE1 0x005922A9 + #define MEM_SDMODE2 0x00000000 + + #define MEM_SDADDR0 0x001003F0 + #define MEM_SDADDR1 0x001043F0 + #define MEM_SDADDR2 0x00000000 + + #define MEM_SDREFCFG_D 0x6400061A /* disable */ + #define MEM_SDREFCFG_E 0x6600061A /* enable */ + #define MEM_SDWRMD0 0x00000023 + #define MEM_SDWRMD1 0x00000023 + #define MEM_SDWRMD2 0x00000000 + + #define MEM_1MS ((396000000/1000000) * 1000) + + /********************************************************************/ + /********************************************************************/ + /********************************************************************/ + /********************************************************************/ + + .set noreorder + + LEAF(sys_init_ekit1) + + #define RA t5 + + /**** Store return address ****/ + move RA, ra + + /* + * Establish Status Register + * (set BEV, clear ERL, clear EXL, clear IE) + */ + li t1, 0x00400000 + mtc0 t1, C0_Status + + /* + * Establish CP0 Config0 + * (set K0=3) + */ + li t1, 0x00000003 + MTC0( t1, C0_Config) + + /* + * Disable Watchpoint facilities + */ + li t1, 0x00000000 + MTC0( t1, C0_WatchLo) + + /* + * Establish EJTAG Debug register + */ + MTC0( zero, C0_Debug) + nop + + /* + * Establish Cause + * (set IV bit) + */ + li t1, 0x00800000 + MTC0( t1, C0_Cause) + + /* Establish Wired (and Random) */ + MTC0( zero, C0_Wired) + nop + + /* + * Establish CPU PLL frequency + */ + li t0, KSEG1BASE + li t1, AU1X00_SYS_BASE + or t0, t0, t1 + li t1, EKIT1100_SYS_CPUPLL + sw t1, AU1X00_SYS_CPUPLL_OFS(t0) + sync + nop + nop + + /* + * Establish system bus divider + */ + li t1, EKIT1100_SYS_POWERCTRL + sw t1, AU1X00_SYS_POWERCTRL_OFS(t0) + sync + + /* + * Establish AUX PLL frequency + */ + li t1, EKIT1100_SYS_AUXPLL + sw t1, AU1X00_SYS_AUXPLL_OFS(t0) + sync + + /* + * Start the 32kHz oscillator + */ + li t1, 0x00000100 + sw t1, AU1X00_SYS_CNTRCTRL_OFS(t0) + sync + + /* + * Initialize static memory controller + */ + li t0, KSEG1BASE + li t1, AU1X00_MEM_BASE + or t0, t0, t1 + /* RCE0 */ + li t1, MEM_STCFG0 + sw t1, AU1X00_MEM_STCFG0_OFS(t0) + li t1, MEM_STTIME0 + sw t1, AU1X00_MEM_STTIME0_OFS(t0) + li t1, MEM_STADDR0 + sw t1, AU1X00_MEM_STADDR0_OFS(t0) + /* RCE1 */ + li t1, MEM_STCFG1 + sw t1, AU1X00_MEM_STCFG1_OFS(t0) + li t1, MEM_STTIME1 + sw t1, AU1X00_MEM_STTIME1_OFS(t0) + li t1, MEM_STADDR1 + sw t1, AU1X00_MEM_STADDR1_OFS(t0) + /* RCE2 */ + li t1, MEM_STCFG2 + sw t1, AU1X00_MEM_STCFG2_OFS(t0) + li t1, MEM_STTIME2 + sw t1, AU1X00_MEM_STTIME2_OFS(t0) + li t1, MEM_STADDR2 + sw t1, AU1X00_MEM_STADDR2_OFS(t0) + /* RCE3 */ + li t1, MEM_STCFG3 + sw t1, AU1X00_MEM_STCFG3_OFS(t0) + li t1, MEM_STTIME3 + sw t1, AU1X00_MEM_STTIME3_OFS(t0) + li t1, MEM_STADDR3 + sw t1, AU1X00_MEM_STADDR3_OFS(t0) + sync + + /* + * Set peripherals to a known state + */ + li t0, AU1X00_IC0_ADDR + li t1, 0xFFFFFFFF + sw t1, ic_cfg0clr(t0) + sw t1, ic_cfg1clr(t0) + sw t1, ic_cfg2clr(t0) + sw t1, ic_srcset(t0) + sw t1, ic_assignset(t0) + sw t1, ic_wakeclr(t0) + sw t1, ic_maskclr(t0) + sw t1, ic_risingclr(t0) + sw t1, ic_fallingclr(t0) + sw zero, ic_testbit(t0) + sync + + li t0, AU1X00_IC1_ADDR + li t1, 0xFFFFFFFF + sw t1, ic_cfg0clr(t0) + sw t1, ic_cfg1clr(t0) + sw t1, ic_cfg2clr(t0) + sw t1, ic_srcset(t0) + sw t1, ic_assignset(t0) + sw t1, ic_wakeclr(t0) + sw t1, ic_maskclr(t0) + sw t1, ic_risingclr(t0) + sw t1, ic_fallingclr(t0) + sw zero, ic_testbit(t0) + sync + + li t0, AU1X00_SYS_ADDR + sw zero, sys_freqctrl0(t0) + sw zero, sys_freqctrl1(t0) + sw zero, sys_clksrc(t0) + sw zero, sys_pininputen(t0) + sync + + li t0, AU1X00_AC97_ADDR + li t1, 0x2 + sw t1, ac97_enable(t0) + sync + + li t0, AU1X00_USBH_ADDR + li t1, usbh_enable + addu t0, t1, t0 + sw zero, 0(t0) + sync + + li t0, AU1X00_USBD_ADDR + sw zero, usbd_enable(t0) + sync + + li t0, AU1X00_MACEN_ADDR + sw zero, macen_mac0(t0) + sync + + li t0, AU1X00_UART0_ADDR + sw zero, uart_enable(t0) + sync + + li t0, AU1X00_UART3_ADDR + sw zero, uart_enable(t0) + sync + + li t0, AU1X00_LCD_ADDR + sw zero, lcd_control(t0) + sync + + /* + * Determine cause of reset + */ + /* wait 10mS to debounce external signals */ + li t1, MEM_1MS*10 + 1: add t1, -1 + bne t1, zero, 1b + nop + + li t0, AU1X00_SYS_ADDR + lw t1, sys_wakesrc(t0) + + /* Clear sys_wakemsk to prevent false events */ + sw zero, sys_wakemsk(t0) + sync + + /* Check for Hardware Reset */ + andi t2, t1, 0x01 + bne zero, t2, hardwarereset + + /* Check for Sleep Wakeup */ + andi t2, t1, 0x02 + bne zero, t2, sleepwakeup + nop + + /* Assume run-time reset */ + b runtimereset + nop + + /********************************************************************/ + + hardwarereset: + /* + * Initialize SDRAM + */ + jal initSDRAM + nop + + /* + * Initialize BOARD-specific items + */ + jal initBOARD + nop + + /* + * Invoke application + */ + b alldone + nop + + /********************************************************************/ + + runtimereset: + /* + * Initialize SDRAM + */ + jal initSDRAM + nop + + /* + * Initialize BOARD-specific items + */ + jal initBOARD + nop + + /* + * Invoke application + */ + b alldone + nop + + /********************************************************************/ + + sleepwakeup: + /* + * Initialize SDRAM. The SDRAM must be in self-refresh mode. + */ + jal wakeupSDRAM + nop + + /* + * Initialize BOARD-specific items + */ + jal initBOARD + nop + + /* + * Invoke application + */ + la t0, AU1X00_SYS_ADDR + lw sp, sys_scratch0(t0) + lw ra, sys_scratch1(t0) + + jr ra + nop + + /********************************************************************/ + + /* + * This routine initializes the SDRAM controller from Initial + * Power-up Reset or Running Reset. + */ + initSDRAM: + + /* Only perform SDRAM init if running from ROM/Flash */ + addu t2, ra, zero /* preserve ra */ + bal getPC + nop + getPC: + lui t0, 0x1F00 /* ROM/flash address? */ + and t1, t0, ra + addu ra, t2, zero /* restore ra */ + bne t0, t1, initSDRAMdone + nop + + /* wait 1mS before setup */ + li t1, MEM_1MS + 1: add t1, -1 + bne t1, zero, 1b + nop + + li t0, AU1X00_MEM_ADDR + li t1, MEM_SDMODE0 + sw t1, mem_sdmode0(t0) + + li t1, MEM_SDMODE1 + sw t1, mem_sdmode1(t0) + + li t1, MEM_SDMODE2 + sw t1, mem_sdmode2(t0) + + li t1, MEM_SDADDR0 + sw t1, mem_sdaddr0(t0) + + li t1, MEM_SDADDR1 + sw t1, mem_sdaddr1(t0) + + li t1, MEM_SDADDR2 + sw t1, mem_sdaddr2(t0) + + sync + + li t1, MEM_SDREFCFG_D + sw t1, mem_sdrefcfg(t0) + sync + + sw zero, mem_sdprecmd(t0) + sync + + sw zero, mem_sdautoref(t0) + sync + + sw zero, mem_sdautoref(t0) + sync + + li t1, MEM_SDREFCFG_E + sw t1, mem_sdrefcfg(t0) + sync + + li t1, MEM_SDWRMD0 + sw t1, mem_sdwrmd0(t0) + sync + + li t1, MEM_SDWRMD1 + sw t1, mem_sdwrmd1(t0) + sync + + li t1, MEM_SDWRMD2 + sw t1, mem_sdwrmd2(t0) + sync + + /* wait 1mS after setup */ + li t1, MEM_1MS + 1: add t1, -1 + bne t1, zero, 1b + nop + + initSDRAMdone: + jr ra + nop + + /********************************************************************/ + + wakeupSDRAM: + + /* + * SDRAM must be in sleep/self refresh mode. For these SDRAMs, + * must assert CKE, then tRC (70ns) of NOPs, then burst refresh + * of all rows prior to using. + */ + li t0, AU1X00_MEM_ADDR + + /* + * Enable SDRAM, assert CKE + */ + li t1, MEM_SDMODE0 + sw t1, mem_sdmode0(t0) + + li t1, MEM_SDMODE1 + sw t1, mem_sdmode1(t0) + + li t1, MEM_SDMODE2 + sw t1, mem_sdmode2(t0) + + li t1, MEM_SDADDR0 + sw t1, mem_sdaddr0(t0) + + li t1, MEM_SDADDR1 + sw t1, mem_sdaddr1(t0) + + li t1, MEM_SDADDR2 + sw t1, mem_sdaddr2(t0) + + /* + * Issue 70ns of NOPs (one Flash access is ~120ns) + * Must use non-cached KSEG1 address of Flash + */ + li t1, 0xBFC00000 + lw t1, 0(t1) + sync + + /* + * Perform burst refresh of 4096 rows + */ + li t1, 4096 + burstrefresh: + sw zero, mem_sdautoref(t0) + bne zero, t1, burstrefresh + addi t1, t1, -1 + + /* + * Re-start auto refresh timer + */ + li t1, MEM_SDREFCFG_E + sw t1, mem_sdrefcfg(t0) + sync + + jr ra + nop + + /********************************************************************/ + + initBOARD: + + /* + * External and/or board-specific peripheral initialization + */ + #define CPLD_ADDR 0xB8000000 + + /* + * Establish MUXed pin functionality + * + * PC=0 PCMCIA signals + * LCD=0 LCD signals + * CS=0 EXTCLK0 + * USB=0 USBD + * U3=0 UART3 + * U1=0 UART1 + * SRC=0 GPIO6 + * EX1=1 EXTCLK1 + * EX0=0 GPIO2 + * IRF=1 IRFIRSEL + * UR3=1 UART3 + * I2D=0 GPIO8 + * I2S=1 GPIO31..29 + * NI=0 MAC0 + * U0=0 UART0 + * IRD=0 IrDA + * A97=0 AC97 + * S0=0 SSI + */ + li t0, AU1X00_SYS_ADDR + li t1, (1<<10)|(1<<8)|(1<<7)|(1<<5) + sw t1, sys_pinfunc(t0) + + /* + * Establish GPIO direction + * + * GPIO0 Input GPIO0(IRQ#) + * GPIO1 Input GPIO1(IRQ#) + * GPIO2 Input GPIO2 + * GPIO3 Output EXTCLK1 + * GPIO4 Input GPIO4 + * GPIO5 Input GPIO5 + * GPIO6 Input GPIO6(IRQ#) + * GPIO7 Output GPIO7(RSTSW#) + * GPIO8 Input GPIO8 + * GPIO9 UART3 + * GPIO10 UART3 + * GPIO11 UART3 + * GPIO12 UART3 + * GPIO13 UART3 + * GPIO14 UART3 + * GPIO15 IrDA + * GPIO16 Input GPIO16(CFOC#) + * GPIO17 Output GPIO17(CFDATA) + * GPIO18 Output GPIO18(CFCLOCK) + * GPIO19 Output GPIO19(CFLATCH) + * GPIO20 Input GPIO20 + * GPIO21 Input GPIO21 + * GPIO22 Input GPIO22 + * GPIO23 Input GPIO23 + * GPIO24 MAC0 + * GPIO25 MAC0 + * GPIO26 MAC0 + * GPIO27 MAC0 + * GPIO28 MAC0 + * GPIO29 Input GPIO29 + * GPIO30 Input GPIO30 + * GPIO31 Input GPIO31 + */ + li t1, 0xE0F10177 + sw t1, sys_trioutclr(t0) + sync + li t1, 0x000E0008 + sw t1, sys_outputclr(t0) + sync + li t1, 0x00000080 + sw t1, sys_outputset(t0) + sync + + /* + * Establish GPIO2 direction + * + * GPIO200 LCD + * GPIO201 LCD + * GPIO202 LCD + * GPIO203 LCD + * GPIO204 PCMCIA + * GPIO205 PCMCIA + * GPIO206 PCMCIA + * GPIO207 PCMCIA + * GPIO208 SSI + * GPIO209 SSI + * GPIO210 SSI + * GPIO211 IrDA + * GPIO212 UART0 + * GPIO213 UART1 + * GPIO214 UART3 + * GPIO215 MAC0 + */ + li t0, AU1X00_GPIO2_ADDR + li t1, 3 + sw t1, gpio2_enable(t0) + sync + li t1, 1 + sw t1, gpio2_enable(t0) + sync + sw zero, gpio2_inten(t0) + sync + sw zero, gpio2_dir(t0) + sync + sw zero, gpio2_output(t0) + sync + + /* + * Establish CLOCKing + * + * FREQ5: unused + * FREQ4: unused + * FREQ3: unused + * FREQ2: USBH, USBD, IrDA, EXTCLK1 + * FREQ1: LCD (not setup here) + * FREQ0: unused + */ + li t0, AU1X00_SYS_ADDR + li t1, (0<<22)|(1<<21)|(1<<20) + sw t1, sys_freqctrl0(t0) + sync + li t1, (4<<27)|(1<<26)|(1<<25)|(4<<2)|(0<<1)|(0<<0) + sw t1, sys_clksrc(t0) + sync + + /* Take AMD PHYs out of reset */ + li t0, KSEG1BASE + li t1, EKIT1100_BCSR_BASE + or t0, t0, t1 + li t1, 0x00000000 + sw t1, EKIT1100_BCSR_SYS_OFS(t0) + sync + + /* Ensure PCMCIA interface disabled */ + li t1, 0x00400000 + sw t1, EKIT1100_BCSR_CF0_OFS(t0) + sync + sw t1, EKIT1100_BCSR_CF1_OFS(t0) + sync + + li t1, 0x00000082 // USB0 .. Device + sw t1, EKIT1100_BCSR_USB1_OFS(t0) + sync + + jr ra + nop + + /********************************************************************/ + + alldone: + /**** Setup return parameters ****/ + li v1, EKIT1100_SYSTEMRAM_SIZE + + jr RA + move v0, zero + + /********************************************************************/ + END(sys_init_ekit1) diff -cNr yamon-sde6/arch/reset/init_cpu_s.S yamon-devdrv/arch/reset/init_cpu_s.S *** yamon-sde6/arch/reset/init_cpu_s.S Wed Mar 24 01:50:28 2004 --- yamon-devdrv/arch/reset/init_cpu_s.S Thu Aug 4 14:44:51 2005 *************** *** 168,173 **** --- 168,181 ---- li t0, MIPS_5KE beq k1, t0, 1f nop + #ifdef _ARCH_DEVDRV_EKIT1100 + // li t0, ALCHEMY_REV1 + // beq k1, t0, 1f + // nop + // li t0, ALCHEMY_REV2 + // beq k1, t0, 1f + // nop + #endif b 2f nop 1: diff -cNr yamon-sde6/arch/reset/init_platform_s.S yamon-devdrv/arch/reset/init_platform_s.S *** yamon-sde6/arch/reset/init_platform_s.S Wed Mar 24 01:50:28 2004 --- yamon-devdrv/arch/reset/init_platform_s.S Wed Aug 3 18:00:53 2005 *************** *** 76,81 **** --- 76,84 ---- #include #include #include + #ifdef _ARCH_DEVDRV_EKIT1100 + #include + #endif /************************************************************************ * Definitions *************** *** 99,105 **** --- 102,175 ---- * sys_platform_early ************************************************************************/ LEAF(sys_platform_early) + #ifdef _ARCH_DEVDRV_EKIT1100 + /* Set k0 = Product ID (determined using REVISION register) */ + li k0, HIKSEG1(MIPS_REVISION) + lw k0, LO_OFFS(MIPS_REVISION)(k0) + srl k0, MIPS_REVISION_PROID_SHF + andi k0, MIPS_REVISION_PROID_MSK >> MIPS_REVISION_PROID_SHF + li k1, PRODUCT_THIRD_PARTY_ID + beq k1, k0, early_ekit1 + nop + + done_unknown: + /* Unknown platform */ + j sys_platform_early_done + li v0, ERROR_PLATFORM_UNKNOWN + + early_ekit1: + li t0, KSEG1BASE + li t1, AU1X00_SYS_BASE + or t0, t0, t1 + li t1, EKIT1100_SYS_CPUPLL # CPU Clock = 396MHz + sw t1, AU1X00_SYS_CPUPLL_OFS(t0) + sync + + li t1, 0x000005A0 # enable U3TXD + sw t1, AU1X00_SYS_PINFUNC_OFS(t0) + sync + + li t0, KSEG1BASE + li t1, EKIT1100_BCSR_BASE # disable reset + or t0, t0, t1 + li t1, 0x00000000 + sw t1, EKIT1100_BCSR_SYS_OFS(t0) + sync + + li t0, KSEG1BASE + li t1, AU1X00_UART3_BASE # disable module and clock + or t0, t0, t1 + sw zero, AU1X00_UART_ENABLE_OFS(t0) + sync + + ori t1, zero, 0x01 # enable clock first + sw t1, AU1X00_UART_ENABLE_OFS(t0) + sync + + ori t1, zero, (0x01 | 0x02) # enable module + sw t1, AU1X00_UART_ENABLE_OFS(t0) + sync + + sw zero, AU1X00_UART_INTEN_OFS(t0) + + ori t1, zero, 0x07 + sw t1, AU1X00_UART_FIFOCTRL_OFS(t0) + + ori t3, zero, 54 # BPS_115200_396 + sw t3, AU1X00_UART_CLKDIV_OFS(t0) + + ori t1, zero, 0x03 # N81 + sw t1, AU1X00_UART_LINECTRL_OFS(t0) + sync + + /* v0 should hold error code */ + addiu v0, zero, 0 + + /* return to init code - initialization is done */ + j sys_platform_early_done /* Return */ + move v0, zero + #else /* Early platform specific initialisation. * Don't use registers other than k0/k1 until after * we have made sure an NMI has not occurred. *************** *** 275,280 **** --- 345,351 ---- + #endif /* #ifdef _ARCH_DEVDRV_EKIT1100 */ END(sys_platform_early) *************** *** 282,287 **** --- 353,372 ---- * sys_init_platform ************************************************************************/ LEAF(sys_init_platform) + #ifdef _ARCH_DEVDRV_EKIT1100 + /* E!Kit-1100 */ + li t0, PRODUCT_THIRD_PARTY_ID + beq k0, t0, 2f + nop + + /* Unknown platform */ + jr ra + li v0, ERROR_PLATFORM_UNKNOWN + 2: + DISP_STR( msg_ekit1 ) + j sys_init_ekit1 + nop + #else move v0, zero *************** *** 338,343 **** --- 423,429 ---- jr ra li v0, ERROR_PLATFORM_UNKNOWN + #endif /* #ifdef _ARCH_DEVDRV_EKIT1100 */ END(sys_init_platform) *************** *** 345,350 **** --- 431,489 ---- * sys_disp_string ************************************************************************/ LEAF(sys_disp_string) + #ifdef _ARCH_DEVDRV_EKIT1100 + /* Remove if you want the debug messages */ + #if 1 + jr ra + nop + #endif + li t7, PRODUCT_THIRD_PARTY_ID + bne k0, t7, disp_string_end + nop + + /* Using UART3 for bringup debug messages */ + li t6, KSEG1BASE + li t5, AU1X00_UART3_BASE + or t6, t6, t5 + disp_string_loop: + lw t5, AU1X00_UART_LINESTAT_OFS(t6) # LSR + andi t5, 0x40 # TE + beq t5, zero, disp_string_loop + nop + + lb t5, 0(t9) + beq t5, zero, 1f + nop + + sw t5, AU1X00_UART_TXDATA_OFS(t6) + beq zero, zero, disp_string_loop + addiu t9, t9, 1 + 1: + lw t5, AU1X00_UART_LINESTAT_OFS(t6) # LSR + andi t5, 0x40 # TE + beq t5, zero, 1b + nop + + li t5,'\r' + sw t5, AU1X00_UART_TXDATA_OFS(t6) + 1: + lw t5, AU1X00_UART_LINESTAT_OFS(t6) # LSR + andi t5, 0x40 # TE + beq t5, zero, 1b + nop + + li t5, '\n' + sw t5, AU1X00_UART_TXDATA_OFS(t6) + 1: + lw t5, AU1X00_UART_LINESTAT_OFS(t6) # LSR + andi t5, 0x40 # TE + beq t5, zero, 1b + nop + + disp_string_end: + jr ra + nop + #else li t7, PRODUCT_ATLASA_ID beq k0, t7, disp_string_atlas_malta *************** *** 405,410 **** --- 544,550 ---- jr ra nop + #endif /* #ifdef _ARCH_DEVDRV_EKIT1100 */ END(sys_disp_string) *************** *** 489,492 **** --- 629,635 ---- MSG( msg_malta, "MALTA" ) MSG( msg_sead, "SEAD" ) MSG( msg_sead2, "SEAD-2" ) + #ifdef _ARCH_DEVDRV_EKIT1100 + MSG( msg_ekit1, "E!Kit-1100" ) + #endif diff -cNr yamon-sde6/arch/shell/platform/shell_platform.c yamon-devdrv/arch/shell/platform/shell_platform.c *** yamon-sde6/arch/shell/platform/shell_platform.c Wed Mar 24 01:50:28 2004 --- yamon-devdrv/arch/shell/platform/shell_platform.c Fri Aug 5 14:59:33 2005 *************** *** 157,162 **** --- 157,174 ---- switch( sys_platform ) { + #ifdef _ARCH_DEVDRV_EKIT1100 + case PRODUCT_THIRD_PARTY_ID: + shell_register_cmd( shell_sample_init() ); + shell_register_cmd( shell_off_init() ); + shell_register_cmd( shell_date_init() ); + shell_register_cmd( shell_reset_init() ); + shell_register_cmd( shell_ping_init() ); + shell_register_cmd( shell_fread_init() ); + shell_register_cmd( shell_fwrite_init() ); + shell_register_cmd( shell_info_init( FALSE, FALSE, TRUE, TRUE, FALSE ) ); + break; + #else case PRODUCT_ATLASA_ID : shell_register_cmd( shell_off_init() ); shell_register_cmd( shell_date_init() ); *************** *** 197,202 **** --- 209,215 ---- shell_register_cmd( shell_reset_init() ); shell_register_cmd( shell_info_init( FALSE, FALSE, FALSE, FALSE, FALSE ) ); break; + #endif /* #ifdef _ARCH_DEVDRV_EKIT1100 */ default : break; } diff -cNr yamon-sde6/arch/syscon/cpu/syscon_cpu.c yamon-devdrv/arch/syscon/cpu/syscon_cpu.c *** yamon-sde6/arch/syscon/cpu/syscon_cpu.c Wed Mar 24 01:50:28 2004 --- yamon-devdrv/arch/syscon/cpu/syscon_cpu.c Thu Aug 4 17:16:08 2005 *************** *** 503,508 **** --- 503,512 ---- case MIPS_M4K : case MIPS_5K : case MIPS_5KE : + #ifdef _ARCH_DEVDRV_EKIT1100 + case ALCHEMY_REV1 : + case ALCHEMY_REV2 : + #endif /* Store initial setting of CP0 CONFIG1 register */ config1 = sys_cp0_read32( R_C0_Config, R_C0_SelConfig1 ); diff -cNr yamon-sde6/arch/syscon/platform/core/syscon_core.c yamon-devdrv/arch/syscon/platform/core/syscon_core.c *** yamon-sde6/arch/syscon/platform/core/syscon_core.c Wed Mar 24 01:50:28 2004 --- yamon-devdrv/arch/syscon/platform/core/syscon_core.c Fri Jul 22 19:38:00 2005 *************** *** 82,87 **** --- 82,90 ---- #include #include #include + #ifdef _ARCH_DEVDRV_EKIT1100 + #include + #endif /************************************************************************ * Definitions *************** *** 1026,1031 **** --- 1029,1039 ---- if (sys_corecard != MIPS_REVISION_CORID_SEAD_MSC01) { syscon_register_id_core( SYSCON_BOARD_CORECARD_NAME_ID, + #ifdef _ARCH_DEVDRV_EKIT1100 + /* E!Kit-1100 */ + NULL, NULL, + NULL, NULL ); + #else /* Galileo based */ syscon_string_read, (sys_corecard == MIPS_REVISION_CORID_CORE_LV) ? *************** *** 1049,1059 **** --- 1057,1073 ---- (sys_corecard == MIPS_REVISION_CORID_CORE_20K) ? name_core_20k : name_core_emul, NULL, NULL ); + #endif /* #ifdef _ARCH_DEVDRV_EKIT1100 */ } /* Names/revision of System controller */ syscon_register_id_core( SYSCON_SYSCTRL_NAME_ID, + #ifdef _ARCH_DEVDRV_EKIT1100 + /* E!Kit-1100 */ + NULL, NULL, + NULL, NULL ); + #else /* Galileo based */ syscon_string_read, (void *)name_galileo, NULL, NULL, *************** *** 1063,1070 **** --- 1077,1090 ---- /* Bonito64 based */ syscon_string_read, (void *)&name_core_bonito[4], NULL, NULL ); + #endif /* #ifdef _ARCH_DEVDRV_EKIT1100 */ syscon_register_id_core( SYSCON_SYSCTRL_REV_ID, + #ifdef _ARCH_DEVDRV_EKIT1100 + /* E!Kit-1100 */ + NULL, NULL, + NULL, NULL ); + #else /* Galileo based */ syscon_string_read, (void *)version_syscntrl, NULL, NULL, *************** *** 1074,1079 **** --- 1094,1100 ---- /* Bonito64 based */ syscon_string_read, (void *)version_syscntrl, NULL, NULL ); + #endif /* #ifdef _ARCH_DEVDRV_EKIT1100 */ /* SDRAM parameters */ *************** *** 1086,1091 **** --- 1107,1117 ---- NULL, NULL ); syscon_register_id_core( SYSCON_BOARD_SYSTEMRAM_REFRESH_NS_CFG_ID, + #ifdef _ARCH_DEVDRV_EKIT1100 + /* E!Kit-1100 */ + NULL, NULL, + NULL, NULL ); + #else /* Galileo based */ board_systemram_refresh_ns_gt64120_read, NULL, board_systemram_refresh_ns_gt64120_write, NULL, *************** *** 1102,1109 **** --- 1128,1141 ---- */ board_systemram_refresh_ns_bonito64_read, NULL, NULL, NULL ); + #endif /* #ifdef _ARCH_DEVDRV_EKIT1100 */ syscon_register_id_core( SYSCON_BOARD_SYSTEMRAM_SRASPRCHG_CYCLES_CFG_ID, + #ifdef _ARCH_DEVDRV_EKIT1100 + /* E!Kit-1100 */ + NULL, NULL, + NULL, NULL ); + #else /* Galileo based */ board_systemram_srasprchg_cycles_gt64120_read, NULL, board_systemram_srasprchg_cycles_gt64120_write, NULL, *************** *** 1113,1120 **** --- 1145,1158 ---- /* Bonito64 based */ board_systemram_srasprchg_cycles_bonito64_read, NULL, board_systemram_srasprchg_cycles_bonito64_write, NULL ); + #endif /* #ifdef _ARCH_DEVDRV_EKIT1100 */ syscon_register_id_core( SYSCON_BOARD_SYSTEMRAM_SRAS2SCAS_CYCLES_CFG_ID, + #ifdef _ARCH_DEVDRV_EKIT1100 + /* E!Kit-1100 */ + NULL, NULL, + NULL, NULL ); + #else /* Galileo based */ board_systemram_sras2scas_cycles_gt64120_read, NULL, board_systemram_sras2scas_cycles_gt64120_write, NULL, *************** *** 1124,1131 **** --- 1162,1175 ---- /* Bonito64 based */ board_systemram_sras2scas_cycles_bonito64_read, NULL, board_systemram_sras2scas_cycles_bonito64_write, NULL ); + #endif /* #ifdef _ARCH_DEVDRV_EKIT1100 */ syscon_register_id_core( SYSCON_BOARD_SYSTEMRAM_CASLAT_CYCLES_CFG_ID, + #ifdef _ARCH_DEVDRV_EKIT1100 + /* E!Kit-1100 */ + NULL, NULL, + NULL, NULL ); + #else /* Galileo based */ board_systemram_caslat_cycles_gt64120_read, NULL, NULL, NULL, *************** *** 1135,1142 **** --- 1179,1192 ---- /* Bonito64 based */ board_systemram_caslat_cycles_bonito64_read, NULL, NULL, NULL ); + #endif /* #ifdef _ARCH_DEVDRV_EKIT1100 */ syscon_register_id_core( SYSCON_BOARD_SYSTEMRAM_READ_BURSTLEN_CFG_ID, + #ifdef _ARCH_DEVDRV_EKIT1100 + /* E!Kit-1100 */ + NULL, NULL, + NULL, NULL ); + #else /* Galileo based */ board_systemram_rw_burstlen_gt64120_read, NULL, NULL, NULL, *************** *** 1146,1153 **** --- 1196,1209 ---- /* Bonito64 based */ board_systemram_rw_burstlen_bonito64_read, NULL, NULL, NULL ); + #endif /* #ifdef _ARCH_DEVDRV_EKIT1100 */ syscon_register_id_core( SYSCON_BOARD_SYSTEMRAM_WRITE_BURSTLEN_CFG_ID, + #ifdef _ARCH_DEVDRV_EKIT1100 + /* E!Kit-1100 */ + NULL, NULL, + NULL, NULL ); + #else /* Galileo based */ board_systemram_rw_burstlen_gt64120_read, NULL, NULL, NULL, *************** *** 1157,1164 **** --- 1213,1226 ---- /* Bonito64 based */ board_systemram_rw_burstlen_bonito64_read, NULL, NULL, NULL ); + #endif /* #ifdef _ARCH_DEVDRV_EKIT1100 */ syscon_register_id_core( SYSCON_BOARD_SYSTEMRAM_CSLAT_CYCLES_CFG_ID, + #ifdef _ARCH_DEVDRV_EKIT1100 + /* E!Kit-1100 */ + NULL, NULL, + NULL, NULL ); + #else /* Galileo based */ NULL, NULL, NULL, NULL, *************** *** 1168,1175 **** --- 1230,1243 ---- /* Bonito64 based */ NULL, NULL, NULL, NULL ); + #endif /* #ifdef _ARCH_DEVDRV_EKIT1100 */ syscon_register_id_core( SYSCON_BOARD_SYSTEMRAM_WRLAT_CYCLES_CFG_ID, + #ifdef _ARCH_DEVDRV_EKIT1100 + /* E!Kit-1100 */ + NULL, NULL, + NULL, NULL ); + #else /* Galileo based */ NULL, NULL, NULL, NULL, *************** *** 1179,1186 **** --- 1247,1260 ---- /* Bonito64 based */ NULL, NULL, NULL, NULL ); + #endif /* #ifdef _ARCH_DEVDRV_EKIT1100 */ syscon_register_id_core( SYSCON_BOARD_SYSTEMRAM_RDDEL_CYCLES_CFG_ID, + #ifdef _ARCH_DEVDRV_EKIT1100 + /* E!Kit-1100 */ + NULL, NULL, + NULL, NULL ); + #else /* Galileo based */ NULL, NULL, NULL, NULL, *************** *** 1190,1197 **** --- 1264,1277 ---- /* Bonito64 based */ NULL, NULL, NULL, NULL ); + #endif /* #ifdef _ARCH_DEVDRV_EKIT1100 */ syscon_register_id_core( SYSCON_BOARD_SYSTEMRAM_DDR_CFG_ID, + #ifdef _ARCH_DEVDRV_EKIT1100 + /* E!Kit-1100 */ + NULL, NULL, + NULL, NULL ); + #else /* Galileo based */ NULL, NULL, NULL, NULL, *************** *** 1201,1208 **** --- 1281,1294 ---- /* Bonito64 based */ NULL, NULL, NULL, NULL ); + #endif /* #ifdef _ARCH_DEVDRV_EKIT1100 */ syscon_register_id_core( SYSCON_BOARD_SYSTEMRAM_FW_CFG_ID, + #ifdef _ARCH_DEVDRV_EKIT1100 + /* E!Kit-1100 */ + NULL, NULL, + NULL, NULL ); + #else /* Galileo based */ NULL, NULL, NULL, NULL, *************** *** 1212,1219 **** --- 1298,1311 ---- /* Bonito64 based */ NULL, NULL, NULL, NULL ); + #endif /* #ifdef _ARCH_DEVDRV_EKIT1100 */ syscon_register_id_core( SYSCON_BOARD_SYSTEMRAM_CLKRAT_CFG_ID, + #ifdef _ARCH_DEVDRV_EKIT1100 + /* E!Kit-1100 */ + NULL, NULL, + NULL, NULL ); + #else /* Galileo based */ NULL, NULL, NULL, NULL, *************** *** 1223,1230 **** --- 1315,1328 ---- /* Bonito64 based */ NULL, NULL, NULL, NULL ); + #endif /* #ifdef _ARCH_DEVDRV_EKIT1100 */ syscon_register_id_core( SYSCON_BOARD_SYSTEMRAM_PARITY_CFG_ID, + #ifdef _ARCH_DEVDRV_EKIT1100 + /* E!Kit-1100 */ + NULL, NULL, + NULL, NULL ); + #else /* Galileo based */ NULL, NULL, NULL, NULL, *************** *** 1234,1241 **** --- 1332,1345 ---- /* Bonito64 based */ NULL, NULL, NULL, NULL ); + #endif /* #ifdef _ARCH_DEVDRV_EKIT1100 */ syscon_register_id_core( SYSCON_SYSCTRL_WC_CFG_ID, + #ifdef _ARCH_DEVDRV_EKIT1100 + /* E!Kit-1100 */ + NULL, NULL, + NULL, NULL ); + #else /* Galileo based */ NULL, NULL, NULL, NULL, *************** *** 1245,1256 **** --- 1349,1366 ---- /* Bonito64 based */ NULL, NULL, NULL, NULL ); + #endif /* #ifdef _ARCH_DEVDRV_EKIT1100 */ syscon_register_generic( SYSCON_SYSCTRL_REGADDR_BASE_ID, board_sysctrl_regaddrbase_generic_read, NULL, NULL, NULL ); syscon_register_id_core( SYSCON_SYSCTRL_SYSID_ID, + #ifdef _ARCH_DEVDRV_EKIT1100 + /* E!Kit-1100 */ + NULL, NULL, + NULL, NULL ); + #else /* Galileo based */ NULL, NULL, NULL, NULL, *************** *** 1260,1267 **** --- 1370,1383 ---- /* Bonito64 based */ NULL, NULL, NULL, NULL ); + #endif /* #ifdef _ARCH_DEVDRV_EKIT1100 */ syscon_register_id_core( SYSCON_SYSCTRL_PBCREV_MAJOR_ID, + #ifdef _ARCH_DEVDRV_EKIT1100 + /* E!Kit-1100 */ + NULL, NULL, + NULL, NULL ); + #else /* Galileo based */ NULL, NULL, NULL, NULL, *************** *** 1271,1278 **** --- 1387,1400 ---- /* Bonito64 based */ NULL, NULL, NULL, NULL ); + #endif /* #ifdef _ARCH_DEVDRV_EKIT1100 */ syscon_register_id_core( SYSCON_SYSCTRL_PBCREV_MINOR_ID, + #ifdef _ARCH_DEVDRV_EKIT1100 + /* E!Kit-1100 */ + NULL, NULL, + NULL, NULL ); + #else /* Galileo based */ NULL, NULL, NULL, NULL, *************** *** 1282,1292 **** --- 1404,1420 ---- /* Bonito64 based */ NULL, NULL, NULL, NULL ); + #endif /* #ifdef _ARCH_DEVDRV_EKIT1100 */ if (sys_corecard == MIPS_REVISION_CORID_SEAD_MSC01) return; syscon_register_id_core( SYSCON_SYSCTRL_PCIREV_MAJOR_ID, + #ifdef _ARCH_DEVDRV_EKIT1100 + /* E!Kit-1100 */ + NULL, NULL, + NULL, NULL ); + #else /* Galileo based */ NULL, NULL, NULL, NULL, *************** *** 1296,1303 **** --- 1424,1437 ---- /* Bonito64 based */ NULL, NULL, NULL, NULL ); + #endif /* #ifdef _ARCH_DEVDRV_EKIT1100 */ syscon_register_id_core( SYSCON_SYSCTRL_PCIREV_MINOR_ID, + #ifdef _ARCH_DEVDRV_EKIT1100 + /* E!Kit-1100 */ + NULL, NULL, + NULL, NULL ); + #else /* Galileo based */ NULL, NULL, NULL, NULL, *************** *** 1307,1312 **** --- 1441,1447 ---- /* Bonito64 based */ NULL, NULL, NULL, NULL ); + #endif /* #ifdef _ARCH_DEVDRV_EKIT1100 */ /* PCI parameters */ *************** *** 1360,1365 **** --- 1495,1507 ---- void syscon_register_id_core( t_syscon_ids id, /* OBJECT ID from syscon_api.h */ + #ifdef _ARCH_DEVDRV_EKIT1100 + /* E!Kit-1100 */ + t_syscon_func read_ekit1, /* Core E!Kit-1100 read */ + void *read_data_ekit1, /* Registered data */ + t_syscon_func write_ekit1, /* Core E!Kit-1100 write */ + void *write_data_ekit1 ) /* Registered data */ + #else /* Galileo based */ t_syscon_func read_galileo, /* Core Galileo read function */ *************** *** 1378,1388 **** --- 1520,1544 ---- void *read_data_bonito64, /* Registered data */ t_syscon_func write_bonito64, /* Core Bonito64 write */ void *write_data_bonito64 ) /* Registered data */ + #endif /* #ifdef _ARCH_DEVDRV_EKIT1100 */ { t_syscon_obj *obj; obj = &syscon_objects[id]; + #ifdef _ARCH_DEVDRV_EKIT1100 + switch( sys_platform ) + { + case PRODUCT_THIRD_PARTY_ID: + obj->read = read_ekit1; + obj->read_data = read_data_ekit1; + obj->write = write_ekit1; + obj->write_data = write_data_ekit1; + return; + default : + break; + } + #else switch( sys_corecard ) { case MIPS_REVISION_CORID_CORE_LV : *************** *** 1421,1425 **** --- 1577,1582 ---- obj->write = NULL; break; } + #endif /* #ifdef _ARCH_DEVDRV_EKIT1100 */ } diff -cNr yamon-sde6/arch/syscon/platform/syscon_platform.c yamon-devdrv/arch/syscon/platform/syscon_platform.c *** yamon-sde6/arch/syscon/platform/syscon_platform.c Wed Mar 24 01:50:28 2004 --- yamon-devdrv/arch/syscon/platform/syscon_platform.c Mon Sep 26 10:29:39 2005 *************** *** 86,91 **** --- 86,94 ---- #include #include #include + #ifdef _ARCH_DEVDRV_EKIT1100 + #include + #endif #include /* Atlas specific */ #include /* Atlas specific */ *************** *** 112,117 **** --- 115,121 ---- static char *name_sead2 = "SEAD-2"; static char *name_malta = "Malta"; static char *name_basic_rtl = "Basic RTL"; + static char *name_ekit1 = "E!Kit-1100"; /* Pointer to array of objects */ static t_syscon_obj *syscon_objects; *************** *** 478,483 **** --- 482,537 ---- /************************************************************************ + * com_en0_major_device_ekit1_read + ************************************************************************/ + static UINT32 + com_en0_major_device_ekit1_read( + void *param, + void *data, + UINT32 size ) + { + /* ekit1 major device number */ + + *(UINT32 *)param = SYS_MAJOR_LAN_AU1X00; + return OK; + } + + /************************************************************************ + * com_en0_minor_device_ekit1_read + ************************************************************************/ + static UINT32 + com_en0_minor_device_ekit1_read( + void *param, + void *data, + UINT32 size ) + { + /* ekit1 minor device number (a sysenv variable) */ + + if(!env_get( "MAC", NULL, param, sizeof(UINT32) )) + *(UINT32 *)param = 0; + + return OK; + } + + /************************************************************************ + * com_en0_mac_addr_ekit1_read + ************************************************************************/ + static UINT32 + com_en0_mac_addr_ekit1_read( + void *param, + void *data, + UINT32 size ) + { + if(env_get("ethaddr", NULL, param, sizeof(t_mac_addr)) ) + return OK; + else + { + return ERROR_SYSCON_UNKNOWN_PARAM; + } + } + + + /************************************************************************ * com_en0_intline_atlas_read ************************************************************************/ static UINT32 *************** *** 768,773 **** --- 822,842 ---- /************************************************************************ + * board_use_default_ekit1_read + ************************************************************************/ + static UINT32 + board_use_default_ekit1_read( + void *param, + void *data, + UINT32 size ) + { + /* No default switch */ + *(UINT32 *)param = 0; + return OK; + } + + + /************************************************************************ * board_softres_atlas_malta_write ************************************************************************/ static UINT32 *************** *** 800,805 **** --- 869,892 ---- /************************************************************************ + * board_softres_ekit1_write + ************************************************************************/ + static UINT32 + board_softres_ekit1_write( + void *param, + void *data, + UINT32 size ) + { + REG(KSEG1(EKIT1100_BCSR_BASE), EKIT1100_BCSR_SYS) = 0x0F; + + void (*f)(void) = (void *)0xBFC00000; + f(); + + return OK; + } + + + /************************************************************************ * board_systemflash_base_atlas_read ************************************************************************/ static UINT32 *************** *** 828,833 **** --- 915,934 ---- /************************************************************************ + * board_systemflash_base_ekit1_read + ************************************************************************/ + static UINT32 + board_systemflash_base_ekit1_read( + void *param, + void *data, + UINT32 size ) + { + *(void **)param = (void *)EKIT1100_SYSTEMFLASH_BASE; + return OK; + } + + + /************************************************************************ * board_systemflash_size_atlas_read ************************************************************************/ static UINT32 *************** *** 856,861 **** --- 957,976 ---- /************************************************************************ + * board_systemflash_size_ekit1_read + ************************************************************************/ + static UINT32 + board_systemflash_size_ekit1_read( + void *param, + void *data, + UINT32 size ) + { + *(UINT32 *)param = EKIT1100_SYSTEMFLASH_SIZE; + return OK; + } + + + /************************************************************************ * board_monitorflash_base_atlas_malta_read ************************************************************************/ static UINT32 *************** *** 870,875 **** --- 985,1004 ---- /************************************************************************ + * board_monitorflash_base_ekit1_read + ************************************************************************/ + static UINT32 + board_monitorflash_base_ekit1_read( + void *param, + void *data, + UINT32 size ) + { + *(void **)param = (void *)EKIT1100_MONITORFLASH_BASE; + return OK; + } + + + /************************************************************************ * board_monitorflash_size_atlas_malta_read ************************************************************************/ static UINT32 *************** *** 884,889 **** --- 1013,1032 ---- /************************************************************************ + * board_monitorflash_size_ekit1_read + ************************************************************************/ + static UINT32 + board_monitorflash_size_ekit1_read( + void *param, + void *data, + UINT32 size ) + { + *(UINT32 *)param = EKIT1100_MONITORFLASH_SIZE; + return OK; + } + + + /************************************************************************ * board_fileflash_base_atlas_malta_read ************************************************************************/ static UINT32 *************** *** 912,917 **** --- 1055,1074 ---- /************************************************************************ + * board_fileflash_base_ekit1_read + ************************************************************************/ + static UINT32 + board_fileflash_base_ekit1_read( + void *param, + void *data, + UINT32 size ) + { + *(void **)param = (void *)EKIT1100_FILEFLASH_BASE; + return OK; + } + + + /************************************************************************ * board_fileflash_size_atlas_malta_read ************************************************************************/ static UINT32 *************** *** 940,945 **** --- 1097,1116 ---- /************************************************************************ + * board_fileflash_size_ekit1_read + ************************************************************************/ + static UINT32 + board_fileflash_size_ekit1_read( + void *param, + void *data, + UINT32 size ) + { + *(UINT32 *)param = EKIT1100_FILEFLASH_SIZE; + return OK; + } + + + /************************************************************************ * board_systemram_base_sead_read ************************************************************************/ static UINT32 *************** *** 954,959 **** --- 1125,1144 ---- /************************************************************************ + * board_systemram_base_ekit1_read + ************************************************************************/ + static UINT32 + board_systemram_base_ekit1_read( + void *param, + void *data, + UINT32 size ) + { + *(void **)param = (void *)EKIT1100_SYSTEMRAM_BASE; + return OK; + } + + + /************************************************************************ * board_systemram_size_sead_read ************************************************************************/ static UINT32 *************** *** 968,973 **** --- 1153,1172 ---- /************************************************************************ + * board_systemram_size_ekit1_read + ************************************************************************/ + static UINT32 + board_systemram_size_ekit1_read( + void *param, + void *data, + UINT32 size ) + { + *(UINT32 *)param = EKIT1100_SYSTEMRAM_SIZE; + return OK; + } + + + /************************************************************************ * board_sram_base_sead_read ************************************************************************/ static UINT32 *************** *** 1192,1197 **** --- 1391,1409 ---- /************************************************************************ + * board_asciiword_ekit1_write + ************************************************************************/ + static UINT32 + board_asciiword_ekit1_write( + void *param, + void *data, + UINT32 size ) + { + return OK; + } + + + /************************************************************************ * board_asciichar_write ************************************************************************/ static UINT32 *************** *** 1203,1208 **** --- 1415,1427 ---- UINT32 tl; UINT8 *ptb; + #ifdef _ARCH_DEVDRV_EKIT1100 + #if 0 + REG(KSEG1(AU1X00_UART3_BASE), AU1X00_UART_TXDATA) = *ptb; + while(!(REG(KSEG1(AU1X00_UART3_BASE), AU1X00_UART_LINESTAT) & 0x40)); + #endif + return OK; + #else tl = ((t_sys_alphanumeric *)param)->posid; ptb = ((t_sys_alphanumeric *)param)->string; *************** *** 1215,1220 **** --- 1434,1440 ---- { return ERROR_SYSCON_INVALID_CHAR_POS; } + #endif /* #ifdef _ARCH_DEVDRV_EKIT1100 */ } *************** *** 1233,1238 **** --- 1453,1473 ---- tl = ((t_sys_alphanumeric *)param)->posid; ptb = ((t_sys_alphanumeric *)param)->string; + #ifdef _ARCH_DEVDRV_EKIT1100 + #if 0 + while (*ptb != '\0') + { + REG(KSEG1(AU1X00_UART3_BASE), AU1X00_UART_TXDATA) = *ptb; + ptb++; + while(!(REG(KSEG1(AU1X00_UART3_BASE), AU1X00_UART_LINESTAT) & 0x40)); + } + REG(KSEG1(AU1X00_UART3_BASE), AU1X00_UART_TXDATA) = '\r'; + while(!(REG(KSEG1(AU1X00_UART3_BASE), AU1X00_UART_LINESTAT) & 0x40)); + REG(KSEG1(AU1X00_UART3_BASE), AU1X00_UART_TXDATA) = '\n'; + while(!(REG(KSEG1(AU1X00_UART3_BASE), AU1X00_UART_LINESTAT) & 0x40)); + #endif + return OK; + #else /* display string */ while( tl < alpha_display_size ) { *************** *** 1262,1267 **** --- 1497,1503 ---- { return ERROR_SYSCON_INVALID_CHAR_POS; } + #endif /* #ifdef _ARCH_DEVDRV_EKIT1100 */ } *************** *** 1331,1336 **** --- 1567,1585 ---- /************************************************************************ + * board_get_millisec_ekit1_read + ************************************************************************/ + static UINT32 + board_get_millisec_ekit1_read( + void *param, + void *data, + UINT32 size ) + { + *(UINT32 *)param = millisec( sys_cpufreq_hz ); + } + + + /************************************************************************ * board_piix4_smb_base_malta_read ************************************************************************/ static UINT32 *************** *** 1426,1431 **** --- 1675,1694 ---- /************************************************************************ + * board_monitorflash_sectorsize_ekit1_read + ************************************************************************/ + static UINT32 + board_monitorflash_sectorsize_ekit1_read( + void *param, + void *data, + UINT32 size ) + { + *(UINT32 *)param = EKIT1100_MONITORFLASH_SECTORSIZE; + return OK; + } + + + /************************************************************************ * board_systemflash_sectorsize_sead_read ************************************************************************/ static UINT32 *************** *** 1440,1445 **** --- 1703,1722 ---- /************************************************************************ + * board_systemflash_sectorsize_ekit1_read + ************************************************************************/ + static UINT32 + board_systemflash_sectorsize_ekit1_read( + void *param, + void *data, + UINT32 size ) + { + *(UINT32 *)param = EKIT1100_SYSTEMFLASH_SECTORSIZE; + return OK; + } + + + /************************************************************************ * board_fileflash_sectorsize_atlas_malta_read ************************************************************************/ static UINT32 *************** *** 1468,1473 **** --- 1745,1764 ---- /************************************************************************ + * board_fileflash_sectorsize_ekit1_read + ************************************************************************/ + static UINT32 + board_fileflash_sectorsize_ekit1_read( + void *param, + void *data, + UINT32 size ) + { + *(UINT32 *)param = EKIT1100_FILEFLASH_SECTORSIZE; + return OK; + } + + + /************************************************************************ * board_systemflash_bankcount_atlas_read ************************************************************************/ static UINT32 *************** *** 1496,1501 **** --- 1787,1806 ---- /************************************************************************ + * board_systemflash_bankcount_ekit1_read + ************************************************************************/ + static UINT32 + board_systemflash_bankcount_ekit1_read( + void *param, + void *data, + UINT32 size ) + { + *(UINT32 *)param = EKIT1100_SYSTEMFLASH_BANKCOUNT; + return OK; + } + + + /************************************************************************ * board_systemflash_blockcount_atlas_read ************************************************************************/ static UINT32 *************** *** 1524,1529 **** --- 1829,1848 ---- /************************************************************************ + * board_systemflash_blockcount_ekit1_read + ************************************************************************/ + static UINT32 + board_systemflash_blockcount_ekit1_read( + void *param, + void *data, + UINT32 size ) + { + *(UINT32 *)param = EKIT1100_SYSTEMFLASH_BLOCKCOUNT; + return OK; + } + + + /************************************************************************ * board_systemflash_write_enable_atlas_write ************************************************************************/ static UINT32 *************** *** 1552,1557 **** --- 1871,1892 ---- /************************************************************************ + * board_systemflash_write_enable_ekit1_write + ************************************************************************/ + static UINT32 + board_systemflash_write_enable_ekit1_write( + void *param, + void *data, + UINT32 size ) + { + /* Revise: There is a write enable on the flash - it is enabled by default + We may want to change to protect the monitor flash */ + + return OK; + } + + + /************************************************************************ * board_systemflash_write_disable_atlas_write ************************************************************************/ static UINT32 *************** *** 1580,1585 **** --- 1915,1934 ---- /************************************************************************ + * board_systemflash_write_disable_ekit1_write + ************************************************************************/ + static UINT32 + board_systemflash_write_disable_ekit1_write( + void *param, + void *data, + UINT32 size ) + { + /* Revise - right now write disable/enable is not used this could be implemented */ + return OK; + } + + + /************************************************************************ * board_brkres_atlas_malta_read ************************************************************************/ static UINT32 *************** *** 1639,1644 **** --- 1988,2009 ---- /************************************************************************ + * board_systemflash_write_protected_ekit1_read + ************************************************************************/ + static UINT32 + board_systemflash_write_protected_ekit1_read( + void *param, + void *data, + UINT32 size ) + { + /* Revise - enable/disable is not implemented at this time */ + + *(UINT32 *)param = 0; + return OK; + } + + + /************************************************************************ * board_pci_freq_atlas_read ************************************************************************/ static UINT32 *************** *** 1812,1817 **** --- 2177,2198 ---- /************************************************************************ + * board_monitorflash_write_protected_ekit1_read + ************************************************************************/ + static UINT32 + board_monitorflash_write_protected_ekit1_read( + void *param, + void *data, + UINT32 size ) + { + /* Revise - write protection is not enabled at this time */ + + *(UINT32 *)param = 0; + return OK; + } + + + /************************************************************************ * board_fileflash_write_protected_sead_read ************************************************************************/ static UINT32 *************** *** 1826,1831 **** --- 2207,2243 ---- /************************************************************************ + * board_fileflash_write_protected_ekit1_read + ************************************************************************/ + static UINT32 + board_fileflash_write_protected_ekit1_read( + void *param, + void *data, + UINT32 size ) + { + /* Revise - write protection is not implemented at this time */ + + *(UINT32 *)param = 0; + return OK; + } + + + /************************************************************************ + * board_psustby_ekit1_write + ************************************************************************/ + static UINT32 + board_psustby_ekit1_write( + void *param, + void *data, + UINT32 size ) + { + REG(KSEG1(EKIT1100_BCSR_BASE), EKIT1100_BCSR_SYS) = 0x200000; + + return OK; + } + + + /************************************************************************ * board_rtc_addr_atlas_read ************************************************************************/ static UINT32 *************** *** 2211,2216 **** --- 2623,2645 ---- switch( sys_platform ) { + #ifdef _ARCH_DEVDRV_EKIT1100 + case PRODUCT_THIRD_PARTY_ID: + syscon_arch_core_init( objects, 0, 0, 0, 0, 0, 0, 0 ); + + syscon_register_generic( SYSCON_COM_EN0_MAC_ADDR_ID, + com_en0_mac_addr_ekit1_read, NULL, + NULL, NULL ); + + syscon_register_generic( SYSCON_BOARD_SYSTEMRAM_BASE_ID, + board_systemram_base_ekit1_read, NULL, + NULL, NULL ); + + syscon_register_generic( SYSCON_BOARD_SYSTEMRAM_SIZE_ID, + board_systemram_size_ekit1_read, NULL, + NULL, NULL ); + break; + #else case PRODUCT_MALTA_ID : case PRODUCT_ATLASA_ID : *************** *** 2339,2344 **** --- 2768,2774 ---- NULL, NULL ); break; + #endif /* #ifdef _ARCH_DEVDRV_EKIT1100 */ default : break; *************** *** 2363,2368 **** --- 2793,2805 ---- NULL, NULL ); syscon_register_id_board( SYSCON_BOARD_PRODUCTNAME_ID, + #ifdef _ARCH_DEVDRV_EKIT1100 + /* E!Kit-1100 */ + board_productname_read, + (void *)name_ekit1, + NULL, + NULL ); + #else /* Atlas */ board_productname_read, (void *)name_atlas, *************** *** 2380,2387 **** --- 2817,2830 ---- (void *)name_malta, NULL, NULL ); + #endif /* #ifdef _ARCH_DEVDRV_EKIT1100 */ syscon_register_id_board( SYSCON_BOARD_NMI_WERR_ID, + #ifdef _ARCH_DEVDRV_EKIT1100 + /* E!Kit-1100 */ + NULL, NULL, + NULL, NULL ); + #else /* Atlas */ board_nmi_werr_atlas_malta_read, NULL, NULL, NULL, *************** *** 2391,2398 **** --- 2834,2847 ---- /* Malta */ board_nmi_werr_atlas_malta_read, NULL, NULL, NULL ); + #endif /* #ifdef _ARCH_DEVDRV_EKIT1100 */ syscon_register_id_board( SYSCON_BOARD_NMI_ACK_ID, + #ifdef _ARCH_DEVDRV_EKIT1100 + /* E!Kit-1100 */ + NULL, NULL, + NULL, NULL ); + #else /* Atlas */ NULL, NULL, board_nmi_ack_atlas_malta_write, NULL, *************** *** 2402,2409 **** --- 2851,2864 ---- /* Malta */ NULL, NULL, board_nmi_ack_atlas_malta_write, NULL ); + #endif /* #ifdef _ARCH_DEVDRV_EKIT1100 */ syscon_register_id_board( SYSCON_BOARD_CORECARDID_ID, + #ifdef _ARCH_DEVDRV_EKIT1100 + /* E!Kit-1100 */ + NULL, NULL, + NULL, NULL ); + #else /* Atlas */ board_corecardid_atlas_malta_read, NULL, NULL, NULL, *************** *** 2413,2420 **** --- 2868,2881 ---- /* Malta */ board_corecardid_atlas_malta_read, NULL, NULL, NULL ); + #endif /* #ifdef _ARCH_DEVDRV_EKIT1100 */ syscon_register_id_board( SYSCON_BOARD_CORECARDREV_ID, + #ifdef _ARCH_DEVDRV_EKIT1100 + /* E!Kit-1100 */ + NULL, NULL, + NULL, NULL ); + #else /* Atlas */ board_corecardrev_atlas_malta_read, NULL, NULL, NULL, *************** *** 2424,2431 **** --- 2885,2898 ---- /* Malta */ board_corecardrev_atlas_malta_read, NULL, NULL, NULL ); + #endif /* #ifdef _ARCH_DEVDRV_EKIT1100 */ syscon_register_id_board( SYSCON_BOARD_FPGAREV_ID, + #ifdef _ARCH_DEVDRV_EKIT1100 + /* E!Kit-1100 */ + NULL, NULL, + NULL, NULL ); + #else /* Atlas */ board_fpgarev_atlas_malta_read, NULL, NULL, NULL, *************** *** 2434,2441 **** --- 2901,2914 ---- NULL, NULL, board_fpgarev_atlas_malta_read, NULL, NULL, NULL ); + #endif /* #ifdef _ARCH_DEVDRV_EKIT1100 */ syscon_register_id_board( SYSCON_BOARD_RTL_ID, + #ifdef _ARCH_DEVDRV_EKIT1100 + /* E!Kit-1100 */ + NULL, NULL, + NULL, NULL ); + #else /* Atlas */ NULL, NULL, NULL, NULL, *************** *** 2445,2452 **** --- 2918,2931 ---- /* Malta */ NULL, NULL, NULL, NULL ); + #endif /* #ifdef _ARCH_DEVDRV_EKIT1100 */ syscon_register_id_board( SYSCON_BOARD_RTL_NAME_ID, + #ifdef _ARCH_DEVDRV_EKIT1100 + /* E!Kit-1100 */ + NULL, NULL, + NULL, NULL ); + #else /* Atlas */ NULL, NULL, NULL, NULL, *************** *** 2456,2463 **** --- 2935,2948 ---- /* Malta */ NULL, NULL, NULL, NULL ); + #endif /* #ifdef _ARCH_DEVDRV_EKIT1100 */ syscon_register_id_board( SYSCON_BOARD_RTLREV_MAJOR_ID, + #ifdef _ARCH_DEVDRV_EKIT1100 + /* E!Kit-1100 */ + NULL, NULL, + NULL, NULL ); + #else /* Atlas */ NULL, NULL, NULL, NULL, *************** *** 2467,2474 **** --- 2952,2965 ---- /* Malta */ NULL, NULL, NULL, NULL ); + #endif /* #ifdef _ARCH_DEVDRV_EKIT1100 */ syscon_register_id_board( SYSCON_BOARD_RTLREV_MINOR_ID, + #ifdef _ARCH_DEVDRV_EKIT1100 + /* E!Kit-1100 */ + NULL, NULL, + NULL, NULL ); + #else /* Atlas */ NULL, NULL, NULL, NULL, *************** *** 2478,2485 **** --- 2969,2982 ---- /* Malta */ NULL, NULL, NULL, NULL ); + #endif /* #ifdef _ARCH_DEVDRV_EKIT1100 */ syscon_register_id_board( SYSCON_BOARD_USE_DEFAULT_ID, + #ifdef _ARCH_DEVDRV_EKIT1100 + /* E!Kit-1100 */ + board_use_default_ekit1_read, NULL, + NULL, NULL ); + #else /* Atlas */ board_use_default_atlas_malta_read, NULL, NULL, NULL, *************** *** 2489,2496 **** --- 2986,2999 ---- /* Malta */ board_use_default_atlas_malta_read, NULL, NULL, NULL ); + #endif /* #ifdef _ARCH_DEVDRV_EKIT1100 */ syscon_register_id_board( SYSCON_BOARD_INIT_BASED_ON_ENV_ID, + #ifdef _ARCH_DEVDRV_EKIT1100 + /* E!Kit-1100 */ + syscon_true_read, NULL, + NULL, NULL ); + #else /* Atlas */ syscon_true_read, NULL, NULL, NULL, *************** *** 2500,2507 **** --- 3003,3018 ---- /* Malta */ syscon_true_read, NULL, NULL, NULL ); + #endif /* #ifdef _ARCH_DEVDRV_EKIT1100 */ syscon_register_id_board( SYSCON_BOARD_SOFTRES_ID, + #ifdef _ARCH_DEVDRV_EKIT1100 + /* E!Kit-1100 */ + NULL, + NULL, + board_softres_ekit1_write, + NULL); + #else /* Atlas */ NULL, NULL, *************** *** 2519,2526 **** --- 3030,3043 ---- NULL, board_softres_atlas_malta_write, NULL ); + #endif /* #ifdef _ARCH_DEVDRV_EKIT1100 */ syscon_register_id_board( SYSCON_BOARD_BRKRES_ID, + #ifdef _ARCH_DEVDRV_EKIT1100 + /* E!Kit-1100 */ + NULL, NULL, + NULL, NULL ); + #else /* Atlas */ board_brkres_atlas_malta_read, NULL, board_brkres_atlas_malta_write, NULL, *************** *** 2529,2536 **** --- 3046,3061 ---- NULL, NULL, board_brkres_atlas_malta_read, NULL, board_brkres_atlas_malta_write, NULL ); + #endif /* #ifdef _ARCH_DEVDRV_EKIT1100 */ syscon_register_id_board( SYSCON_BOARD_PSUSTBY_ID, + #ifdef _ARCH_DEVDRV_EKIT1100 + /* E!Kit-1100 */ + NULL, + NULL, + board_psustby_ekit1_write, + NULL ); + #else /* Atlas */ NULL, NULL, *************** *** 2556,2563 **** --- 3081,3094 ---- NULL, NULL ); #endif + #endif /* #ifdef _ARCH_DEVDRV_EKIT1100 */ syscon_register_id_board( SYSCON_BOARD_SYSTEMFLASH_BASE_ID, + #ifdef _ARCH_DEVDRV_EKIT1100 + /* E!Kit-1100 */ + board_systemflash_base_ekit1_read, NULL, + NULL, NULL ); + #else /* Atlas */ board_systemflash_base_atlas_read, NULL, NULL, NULL, *************** *** 2567,2574 **** --- 3098,3111 ---- /* Malta */ NULL, NULL, NULL, NULL ); + #endif /* #ifdef _ARCH_DEVDRV_EKIT1100 */ syscon_register_id_board( SYSCON_BOARD_SYSTEMFLASH_SIZE_ID, + #ifdef _ARCH_DEVDRV_EKIT1100 + /* E!Kit-1100 */ + board_systemflash_size_ekit1_read, NULL, + NULL, NULL ); + #else /* Atlas */ board_systemflash_size_atlas_read, NULL, NULL, NULL, *************** *** 2578,2585 **** --- 3115,3128 ---- /* Malta */ NULL, NULL, NULL, NULL ); + #endif /* #ifdef _ARCH_DEVDRV_EKIT1100 */ syscon_register_id_board( SYSCON_BOARD_MONITORFLASH_BASE_ID, + #ifdef _ARCH_DEVDRV_EKIT1100 + /* E!Kit-1100 */ + board_monitorflash_base_ekit1_read, NULL, + NULL, NULL ); + #else /* Atlas */ board_monitorflash_base_atlas_malta_read, NULL, NULL, NULL, *************** *** 2589,2596 **** --- 3132,3145 ---- /* Malta */ board_monitorflash_base_atlas_malta_read, NULL, NULL, NULL ); + #endif /* #ifdef _ARCH_DEVDRV_EKIT1100 */ syscon_register_id_board( SYSCON_BOARD_MONITORFLASH_SIZE_ID, + #ifdef _ARCH_DEVDRV_EKIT1100 + /* E!Kit-1100 */ + board_monitorflash_size_ekit1_read, NULL, + NULL, NULL ); + #else /* Atlas */ board_monitorflash_size_atlas_malta_read, NULL, NULL, NULL, *************** *** 2600,2607 **** --- 3149,3162 ---- /* Malta */ board_monitorflash_size_atlas_malta_read, NULL, NULL, NULL ); + #endif /* #ifdef _ARCH_DEVDRV_EKIT1100 */ syscon_register_id_board( SYSCON_BOARD_FILEFLASH_BASE_ID, + #ifdef _ARCH_DEVDRV_EKIT1100 + /* E!Kit-1100 */ + board_fileflash_base_ekit1_read, NULL, + NULL, NULL ); + #else /* Atlas */ board_fileflash_base_atlas_malta_read, NULL, NULL, NULL, *************** *** 2611,2618 **** --- 3166,3179 ---- /* Malta */ board_fileflash_base_atlas_malta_read, NULL, NULL, NULL ); + #endif /* #ifdef _ARCH_DEVDRV_EKIT1100 */ syscon_register_id_board( SYSCON_BOARD_FILEFLASH_SIZE_ID, + #ifdef _ARCH_DEVDRV_EKIT1100 + /* E!Kit-1100 */ + board_fileflash_size_ekit1_read, NULL, + NULL, NULL ); + #else /* Atlas */ board_fileflash_size_atlas_malta_read, NULL, NULL, NULL, *************** *** 2622,2629 **** --- 3183,3196 ---- /* Malta */ board_fileflash_size_atlas_malta_read, NULL, NULL, NULL ); + #endif /* #ifdef _ARCH_DEVDRV_EKIT1100 */ syscon_register_id_board( SYSCON_BOARD_SRAM_BASE_ID, + #ifdef _ARCH_DEVDRV_EKIT1100 + /* E!Kit-1100 */ + NULL, NULL, + NULL, NULL ); + #else /* Atlas */ NULL, NULL, NULL, NULL, *************** *** 2633,2640 **** --- 3200,3213 ---- /* Malta */ NULL, NULL, NULL, NULL ); + #endif /* #ifdef _ARCH_DEVDRV_EKIT1100 */ syscon_register_id_board( SYSCON_BOARD_SRAM_SIZE_ID, + #ifdef _ARCH_DEVDRV_EKIT1100 + /* E!Kit-1100 */ + NULL, NULL, + NULL, NULL ); + #else /* Atlas */ NULL, NULL, NULL, NULL, *************** *** 2644,2651 **** --- 3217,3230 ---- /* Malta */ NULL, NULL, NULL, NULL ); + #endif /* #ifdef _ARCH_DEVDRV_EKIT1100 */ syscon_register_id_board( SYSCON_BOARD_GT64120_BASE_ID, + #ifdef _ARCH_DEVDRV_EKIT1100 + /* E!Kit-1100 */ + NULL, NULL, + NULL, NULL ); + #else /* Atlas */ board_gt64120_base_atlas_malta_read, NULL, NULL, NULL, *************** *** 2655,2662 **** --- 3234,3247 ---- /* Malta */ board_gt64120_base_atlas_malta_read, NULL, NULL, NULL ); + #endif /* #ifdef _ARCH_DEVDRV_EKIT1100 */ syscon_register_id_board( SYSCON_BOARD_SAA9730_BASE_ID, + #ifdef _ARCH_DEVDRV_EKIT1100 + /* E!Kit-1100 */ + NULL, NULL, + NULL, NULL ); + #else /* Atlas */ board_saa9730_base_atlas_read, NULL, NULL, NULL, *************** *** 2666,2674 **** --- 3251,3265 ---- /* Malta */ NULL, NULL, NULL, NULL ); + #endif /* #ifdef _ARCH_DEVDRV_EKIT1100 */ /* TBD */ syscon_register_id_board( SYSCON_BOARD_SYM53C810A_BASE_ID, + #ifdef _ARCH_DEVDRV_EKIT1100 + /* E!Kit-1100 */ + NULL, NULL, + NULL, NULL ); + #else /* Atlas */ NULL, NULL, NULL, NULL, *************** *** 2678,2686 **** --- 3269,3283 ---- /* Malta */ NULL, NULL, NULL, NULL ); + #endif /* #ifdef _ARCH_DEVDRV_EKIT1100 */ /* TBD */ syscon_register_id_board( SYSCON_BOARD_INTEL21150_BASE_ID, + #ifdef _ARCH_DEVDRV_EKIT1100 + /* E!Kit-1100 */ + NULL, NULL, + NULL, NULL ); + #else /* Atlas */ NULL, NULL, NULL, NULL, *************** *** 2690,2697 **** --- 3287,3300 ---- /* Malta */ NULL, NULL, NULL, NULL ); + #endif /* #ifdef _ARCH_DEVDRV_EKIT1100 */ syscon_register_id_board( SYSCON_BOARD_ICTA_BASE_ID, + #ifdef _ARCH_DEVDRV_EKIT1100 + /* E!Kit-1100 */ + NULL, NULL, + NULL, NULL ); + #else /* Atlas */ board_icta_base_atlas_read, NULL, NULL, NULL, *************** *** 2701,2708 **** --- 3304,3317 ---- /* Malta */ NULL, NULL, NULL, NULL ); + #endif /* #ifdef _ARCH_DEVDRV_EKIT1100 */ syscon_register_id_board( SYSCON_BOARD_TMRA_BASE_ID, + #ifdef _ARCH_DEVDRV_EKIT1100 + /* E!Kit-1100 */ + NULL, NULL, + NULL, NULL ); + #else /* Atlas */ board_tmra_base_atlas_read, NULL, NULL, NULL, *************** *** 2712,2719 **** --- 3321,3334 ---- /* Malta */ NULL, NULL, NULL, NULL ); + #endif /* #ifdef _ARCH_DEVDRV_EKIT1100 */ syscon_register_id_board( SYSCON_BOARD_AM79C973_BASE_ID, + #ifdef _ARCH_DEVDRV_EKIT1100 + /* E!Kit-1100 */ + NULL, NULL, + NULL, NULL ); + #else /* Atlas */ NULL, NULL, NULL, NULL, *************** *** 2723,2730 **** --- 3338,3351 ---- /* Malta */ board_am79c973_base_malta_read, NULL, NULL, NULL ); + #endif /* #ifdef _ARCH_DEVDRV_EKIT1100 */ syscon_register_id_board( SYSCON_BOARD_LEDGREEN_ID, + #ifdef _ARCH_DEVDRV_EKIT1100 + /* E!Kit-1100 */ + NULL, NULL, + NULL, NULL ); + #else /* Atlas */ board_ledgreen_atlas_read, NULL, board_ledgreen_atlas_write, NULL, *************** *** 2734,2741 **** --- 3355,3368 ---- /* Malta */ NULL, NULL, NULL, NULL ); + #endif /* #ifdef _ARCH_DEVDRV_EKIT1100 */ syscon_register_id_board( SYSCON_BOARD_LEDBAR_ID, + #ifdef _ARCH_DEVDRV_EKIT1100 + /* E!Kit-1100 */ + NULL, NULL, + NULL, NULL ); + #else /* Atlas */ board_ledbar_atlas_malta_read, NULL, board_ledbar_atlas_malta_write, NULL, *************** *** 2745,2752 **** --- 3372,3385 ---- /* Malta */ board_ledbar_atlas_malta_read, NULL, board_ledbar_atlas_malta_write, NULL ); + #endif /* #ifdef _ARCH_DEVDRV_EKIT1100 */ syscon_register_id_board( SYSCON_BOARD_ASCIIWORD_ID, + #ifdef _ARCH_DEVDRV_EKIT1100 + /* E!Kit-1100 */ + NULL, NULL, + board_asciiword_ekit1_write, NULL); + #else /* Atlas */ NULL, NULL, board_asciiword_atlas_malta_write, NULL, *************** *** 2756,2763 **** --- 3389,3402 ---- /* Malta */ NULL, NULL, board_asciiword_atlas_malta_write, NULL ); + #endif /* #ifdef _ARCH_DEVDRV_EKIT1100 */ syscon_register_id_board( SYSCON_BOARD_ASCIICHAR_ID, + #ifdef _ARCH_DEVDRV_EKIT1100 + /* E!Kit-1100 */ + NULL, NULL, + board_asciichar_write, NULL ); + #else /* Atlas */ NULL, NULL, board_asciichar_write, NULL, *************** *** 2767,2774 **** --- 3406,3419 ---- /* Malta */ NULL, NULL, board_asciichar_write, NULL ); + #endif /* #ifdef _ARCH_DEVDRV_EKIT1100 */ syscon_register_id_board( SYSCON_BOARD_ASCIISTRING_ID, + #ifdef _ARCH_DEVDRV_EKIT1100 + /* E!Kit-1100 */ + NULL, NULL, + board_asciistring_write, NULL ); + #else /* Atlas */ NULL, NULL, board_asciistring_write, NULL, *************** *** 2778,2785 **** --- 3423,3436 ---- /* Malta */ NULL, NULL, board_asciistring_write, NULL ); + #endif /* #ifdef _ARCH_DEVDRV_EKIT1100 */ syscon_register_id_board( SYSCON_BOARD_GET_MILLISEC_ID, + #ifdef _ARCH_DEVDRV_EKIT1100 + /* E!Kit-1100 */ + board_get_millisec_ekit1_read, NULL, + NULL, NULL ); + #else /* Atlas */ board_get_millisec_atlas_malta_read, NULL, NULL, NULL, *************** *** 2789,2796 **** --- 3440,3453 ---- /* Malta */ board_get_millisec_atlas_malta_read, NULL, NULL, NULL ); + #endif /* #ifdef _ARCH_DEVDRV_EKIT1100 */ syscon_register_id_board( SYSCON_BOARD_SYSTEMFLASH_SECTORSIZE_ID, + #ifdef _ARCH_DEVDRV_EKIT1100 + /* E!Kit-1100 */ + board_systemflash_sectorsize_ekit1_read, NULL, + NULL, NULL ); + #else /* Atlas */ board_systemflash_sectorsize_atlas_read, NULL, NULL, NULL, *************** *** 2800,2807 **** --- 3457,3470 ---- /* Malta */ NULL, NULL, NULL, NULL ); + #endif /* #ifdef _ARCH_DEVDRV_EKIT1100 */ syscon_register_id_board( SYSCON_BOARD_MONITORFLASH_SECTORSIZE_ID, + #ifdef _ARCH_DEVDRV_EKIT1100 + /* E!Kit-1100 */ + board_monitorflash_sectorsize_ekit1_read, NULL, + NULL, NULL ); + #else /* Atlas */ board_monitorflash_sectorsize_atlas_read, NULL, NULL, NULL, *************** *** 2811,2818 **** --- 3474,3487 ---- /* Malta */ board_monitorflash_sectorsize_malta_read, NULL, NULL, NULL ); + #endif /* #ifdef _ARCH_DEVDRV_EKIT1100 */ syscon_register_id_board( SYSCON_BOARD_FILEFLASH_SECTORSIZE_ID, + #ifdef _ARCH_DEVDRV_EKIT1100 + /* E!Kit-1100 */ + board_fileflash_sectorsize_ekit1_read, NULL, + NULL, NULL ); + #else /* Atlas */ board_fileflash_sectorsize_atlas_malta_read, NULL, NULL, NULL, *************** *** 2822,2829 **** --- 3491,3504 ---- /* Malta */ board_fileflash_sectorsize_atlas_malta_read, NULL, NULL, NULL ); + #endif /* #ifdef _ARCH_DEVDRV_EKIT1100 */ syscon_register_id_board( SYSCON_BOARD_SYSTEMFLASH_BANKCOUNT_ID, + #ifdef _ARCH_DEVDRV_EKIT1100 + /* E!Kit-1100 */ + board_systemflash_bankcount_ekit1_read, NULL, + NULL, NULL ); + #else /* Atlas */ board_systemflash_bankcount_atlas_read, NULL, NULL, NULL, *************** *** 2833,2840 **** --- 3508,3521 ---- /* Malta */ NULL, NULL, NULL, NULL ); + #endif /* #ifdef _ARCH_DEVDRV_EKIT1100 */ syscon_register_id_board( SYSCON_BOARD_SYSTEMFLASH_BLOCKCOUNT_ID, + #ifdef _ARCH_DEVDRV_EKIT1100 + /* E!Kit-1100 */ + board_systemflash_blockcount_ekit1_read, NULL, + NULL, NULL ); + #else /* Atlas */ board_systemflash_blockcount_atlas_read, NULL, NULL, NULL, *************** *** 2844,2851 **** --- 3525,3538 ---- /* Malta */ NULL, NULL, NULL, NULL ); + #endif /* #ifdef _ARCH_DEVDRV_EKIT1100 */ syscon_register_id_board( SYSCON_BOARD_SYSTEMFLASH_WRITE_ENABLE_ID, + #ifdef _ARCH_DEVDRV_EKIT1100 + /* E!Kit-1100 */ + NULL, NULL, + board_systemflash_write_enable_ekit1_write, NULL); + #else /* Atlas */ NULL, NULL, board_systemflash_write_enable_atlas_write, NULL, *************** *** 2855,2862 **** --- 3542,3555 ---- /* Malta */ NULL, NULL, NULL, NULL ); + #endif /* #ifdef _ARCH_DEVDRV_EKIT1100 */ syscon_register_id_board( SYSCON_BOARD_SYSTEMFLASH_WRITE_DISABLE_ID, + #ifdef _ARCH_DEVDRV_EKIT1100 + /* E!Kit-1100 */ + NULL, NULL, + board_systemflash_write_disable_ekit1_write, NULL); + #else /* Atlas */ NULL, NULL, board_systemflash_write_disable_atlas_write, NULL, *************** *** 2866,2873 **** --- 3559,3572 ---- /* Malta */ NULL, NULL, NULL, NULL ); + #endif /* #ifdef _ARCH_DEVDRV_EKIT1100 */ syscon_register_id_board( SYSCON_BOARD_SYSTEMFLASH_WRITE_PROTECTED_ID, + #ifdef _ARCH_DEVDRV_EKIT1100 + /* E!Kit-1100 */ + board_systemflash_write_protected_ekit1_read, NULL, + NULL, NULL ); + #else /* Atlas */ board_systemflash_write_protected_atlas_read, NULL, NULL, NULL, *************** *** 2877,2884 **** --- 3576,3589 ---- /* Malta */ NULL, NULL, NULL, NULL ); + #endif /* #ifdef _ARCH_DEVDRV_EKIT1100 */ syscon_register_id_board( SYSCON_BOARD_MONITORFLASH_WRITE_PROTECTED_ID, + #ifdef _ARCH_DEVDRV_EKIT1100 + /* E!Kit-1100 */ + board_monitorflash_write_protected_ekit1_read, NULL, + NULL, NULL ); + #else /* Atlas */ board_monitorflash_write_protected_atlas_malta_read, NULL, NULL, NULL, *************** *** 2888,2895 **** --- 3593,3606 ---- /* Malta */ board_monitorflash_write_protected_atlas_malta_read, NULL, NULL, NULL ); + #endif /* #ifdef _ARCH_DEVDRV_EKIT1100 */ syscon_register_id_board( SYSCON_BOARD_FILEFLASH_WRITE_PROTECTED_ID, + #ifdef _ARCH_DEVDRV_EKIT1100 + /* E!Kit-1100 */ + board_fileflash_write_protected_ekit1_read, NULL, + NULL, NULL ); + #else /* Atlas */ board_fileflash_write_protected_atlas_malta_read, NULL, NULL, NULL, *************** *** 2899,2906 **** --- 3610,3623 ---- /* Malta */ board_fileflash_write_protected_atlas_malta_read, NULL, NULL, NULL ); + #endif /* #ifdef _ARCH_DEVDRV_EKIT1100 */ syscon_register_id_board( SYSCON_BOARD_PCI_FREQ_KHZ_ID, + #ifdef _ARCH_DEVDRV_EKIT1100 + /* E!Kit-1100 */ + NULL, NULL, + NULL, NULL ); + #else /* Atlas */ board_pci_freq_atlas_read, NULL, NULL, NULL, *************** *** 2910,2917 **** --- 3627,3640 ---- /* Malta */ board_pci_freq_malta_read, NULL, NULL, NULL ); + #endif /* #ifdef _ARCH_DEVDRV_EKIT1100 */ syscon_register_id_board( SYSCON_BOARD_PCI_ALLOC_ERR_ID, + #ifdef _ARCH_DEVDRV_EKIT1100 + /* E!Kit-1100 */ + NULL, NULL, + NULL, NULL ); + #else /* Atlas */ board_pci_alloc_err_read, NULL, NULL, NULL, *************** *** 2921,2928 **** --- 3644,3657 ---- /* Malta */ board_pci_alloc_err_read, NULL, NULL, NULL ); + #endif /* #ifdef _ARCH_DEVDRV_EKIT1100 */ syscon_register_id_board( SYSCON_BOARD_RTC_ADDR_ID, + #ifdef _ARCH_DEVDRV_EKIT1100 + /* E!Kit-1100 */ + NULL, NULL, + NULL, NULL ); + #else /* Atlas */ board_rtc_addr_atlas_read, NULL, NULL, NULL, *************** *** 2932,2939 **** --- 3661,3674 ---- /* Malta */ board_rtc_addr_malta_read, NULL, NULL, NULL ); + #endif /* #ifdef _ARCH_DEVDRV_EKIT1100 */ syscon_register_id_board( SYSCON_BOARD_RTC_DATA_ID, + #ifdef _ARCH_DEVDRV_EKIT1100 + /* E!Kit-1100 */ + NULL, NULL, + NULL, NULL ); + #else /* Atlas */ board_rtc_data_atlas_read, NULL, NULL, NULL, *************** *** 2943,2950 **** --- 3678,3691 ---- /* Malta */ board_rtc_data_malta_read, NULL, NULL, NULL ); + #endif /* #ifdef _ARCH_DEVDRV_EKIT1100 */ syscon_register_id_board( SYSCON_BOARD_RTC_REG_SIZE_ID, + #ifdef _ARCH_DEVDRV_EKIT1100 + /* E!Kit-1100 */ + NULL, NULL, + NULL, NULL ); + #else /* Atlas */ syscon_uint8_read, &size32, NULL, NULL, *************** *** 2954,2961 **** --- 3695,3708 ---- /* Malta */ syscon_uint8_read, &size8, NULL, NULL ); + #endif /* #ifdef _ARCH_DEVDRV_EKIT1100 */ syscon_register_id_board( SYSCON_BOARD_EEPROM_ADDR, + #ifdef _ARCH_DEVDRV_EKIT1100 + /* E!Kit-1100 */ + NULL, NULL, + NULL, NULL ); + #else /* Atlas */ board_eeprom_addr_atlas_malta_read, NULL, NULL, NULL, *************** *** 2965,2973 **** --- 3712,3726 ---- /* Malta */ board_eeprom_addr_atlas_malta_read, NULL, NULL, NULL ); + #endif /* #ifdef _ARCH_DEVDRV_EKIT1100 */ syscon_register_id_board( SYSCON_BOARD_EEPROM_SPD_ADDR, + #ifdef _ARCH_DEVDRV_EKIT1100 + /* E!Kit-1100 */ + NULL, NULL, + NULL, NULL ); + #else /* Atlas */ board_eeprom_spd_addr_atlas_malta_read, NULL, NULL, NULL, *************** *** 2977,2984 **** --- 3730,3743 ---- /* Malta */ board_eeprom_spd_addr_atlas_malta_read, NULL, NULL, NULL ); + #endif /* #ifdef _ARCH_DEVDRV_EKIT1100 */ syscon_register_id_board( SYSCON_COM_IIC_BAUDRATE_ID, + #ifdef _ARCH_DEVDRV_EKIT1100 + /* E!Kit-1100 */ + NULL, NULL, + NULL, NULL ); + #else /* Atlas */ com_iic_baudrate_atlas_read, NULL, NULL, NULL, *************** *** 2988,2995 **** --- 3747,3760 ---- /* Malta */ NULL, NULL, NULL, NULL ); + #endif /* #ifdef _ARCH_DEVDRV_EKIT1100 */ syscon_register_id_board( SYSCON_BOARD_PIIX4_SMB_BASE_ID, + #ifdef _ARCH_DEVDRV_EKIT1100 + /* E!Kit-1100 */ + NULL, NULL, + NULL, NULL ); + #else /* Atlas */ NULL, NULL, NULL, NULL, *************** *** 2999,3006 **** --- 3764,3777 ---- /* Malta */ board_piix4_smb_base_malta_read, NULL, NULL, NULL ); + #endif /* #ifdef _ARCH_DEVDRV_EKIT1100 */ syscon_register_id_board( SYSCON_BOARD_PIIX4_POWER_BASE_ID, + #ifdef _ARCH_DEVDRV_EKIT1100 + /* E!Kit-1100 */ + NULL, NULL, + NULL, NULL ); + #else /* Atlas */ NULL, NULL, NULL, NULL, *************** *** 3010,3017 **** --- 3781,3794 ---- /* Malta */ board_piix4_power_base_malta_read, NULL, NULL, NULL ); + #endif /* #ifdef _ARCH_DEVDRV_EKIT1100 */ syscon_register_id_board( SYSCON_COM_PIIX4_IIC_BIGEND_ID, + #ifdef _ARCH_DEVDRV_EKIT1100 + /* E!Kit-1100 */ + NULL, NULL, + NULL, NULL ); + #else /* Atlas */ NULL, NULL, NULL, NULL, *************** *** 3021,3028 **** --- 3798,3811 ---- /* Malta (PCI is always little endian) */ syscon_false_read, NULL, NULL, NULL ); + #endif /* #ifdef _ARCH_DEVDRV_EKIT1100 */ syscon_register_id_board( SYSCON_COM_EN0_MAJOR_DEVICE_ID, + #ifdef _ARCH_DEVDRV_EKIT1100 + /* E!Kit-1100 */ + com_en0_major_device_ekit1_read, NULL, + NULL, NULL ); + #else /* Atlas */ com_en0_major_device_atlas_read, NULL, NULL, NULL, *************** *** 3032,3039 **** --- 3815,3828 ---- /* Malta */ com_en0_major_device_malta_read, NULL, NULL, NULL ); + #endif /* #ifdef _ARCH_DEVDRV_EKIT1100 */ syscon_register_id_board( SYSCON_COM_EN0_IC_ID, + #ifdef _ARCH_DEVDRV_EKIT1100 + /* E!Kit-1100 */ + com_en0_minor_device_ekit1_read, NULL, + NULL, NULL ); + #else /* Atlas */ syscon_true_read, NULL, NULL, NULL, *************** *** 3043,3050 **** --- 3832,3845 ---- /* Malta */ syscon_true_read, NULL, NULL, NULL ); + #endif /* #ifdef _ARCH_DEVDRV_EKIT1100 */ syscon_register_id_board( SYSCON_COM_EN0_INTLINE_ID, + #ifdef _ARCH_DEVDRV_EKIT1100 + /* E!Kit-1100 */ + NULL, NULL, + NULL, NULL ); + #else /* Atlas */ com_en0_intline_atlas_read, NULL, NULL, NULL, *************** *** 3054,3059 **** --- 3849,3855 ---- /* Malta */ com_en0_intline_malta_read, NULL, NULL, NULL ); + #endif /* #ifdef _ARCH_DEVDRV_EKIT1100 */ syscon_register_generic( SYSCON_BOARD_EEPROM_COUNT_ID, syscon_uint8_read, (void *)&eeprom_count, *************** *** 3089,3094 **** --- 3885,3897 ---- void syscon_register_id_board( t_syscon_ids id, /* OBJECT ID from syscon_api.h */ + #ifdef _ARCH_DEVDRV_EKIT1100 + /* E!Kit-1100 */ + t_syscon_func read_ekit1, /* E!Kit-1100 read function */ + void *read_data_ekit1, /* Registered data */ + t_syscon_func write_ekit1, /* E!Kit-1100 write function */ + void *write_data_ekit1 ) /* Registered data */ + #else /* Atlas */ t_syscon_func read_atlas, /* Atlas read function */ void *read_data_atlas, /* Registered data */ *************** *** 3104,3109 **** --- 3907,3913 ---- void *read_data_malta, /* Registered data */ t_syscon_func write_malta, /* Malta write function */ void *write_data_malta ) /* Registered data */ + #endif /* #ifdef _ARCH_DEVDRV_EKIT1100 */ { t_syscon_obj *obj; *************** *** 3111,3116 **** --- 3915,3928 ---- switch( sys_platform ) { + #ifdef _ARCH_DEVDRV_EKIT1100 + case PRODUCT_THIRD_PARTY_ID: + obj->read = read_ekit1; + obj->read_data = read_data_ekit1; + obj->write = write_ekit1; + obj->write_data = write_data_ekit1; + break; + #else case PRODUCT_ATLASA_ID : obj->read = read_atlas; obj->read_data = read_data_atlas; *************** *** 3130,3135 **** --- 3942,3948 ---- obj->write = write_malta; obj->write_data = write_data_malta; break; + #endif /* #ifdef _ARCH_DEVDRV_EKIT1100 */ default : /* Should not happen */ obj->read = NULL; obj->write = NULL; diff -cNr yamon-sde6/arch/syscon/platform/syscon_platform_tty.c yamon-devdrv/arch/syscon/platform/syscon_platform_tty.c *** yamon-sde6/arch/syscon/platform/syscon_platform_tty.c Wed Mar 24 01:50:28 2004 --- yamon-devdrv/arch/syscon/platform/syscon_platform_tty.c Thu Sep 22 14:05:31 2005 *************** *** 81,86 **** --- 81,89 ---- #include #include #include /* Atlas specific */ + #ifdef _ARCH_DEVDRV_EKIT1100 + #include + #endif /************************************************************************ * Definitions *************** *** 118,123 **** --- 121,131 ---- static UINT32 intline_malta_ti16550_1 = MALTA_INTLINE_TTY1; static UINT32 intline_malta_ti16550_2 = (S_StatusIM4 - S_StatusIM); + /* Pb1000 */ + static UINT32 intline_ekit1_tty0 = AU1X00_UART0_INT; + static UINT32 intline_ekit1_tty1 = AU1X00_UART1_INT; + static UINT32 intline_ekit1_tty2 = AU1X00_UART3_INT; + /* Major/minor device number mappings : * * TTY0 TTY1 *************** *** 143,148 **** --- 151,163 ---- static UINT32 malta_major_tty1 = SYS_MAJOR_SERIAL_TI16550; static UINT32 malta_minor_tty1 = SERIAL_MINOR_TI16550_UART1; + /* Only uart0 and uart3 are common on Pb/Db1x000 boards, so map: + YAMON tty0 = uart0; YAMON tty1 = uart3 */ + static UINT32 ekit1_major_tty0 = SYS_MAJOR_SERIAL_AU1X00; + static UINT32 ekit1_minor_tty0 = SERIAL_MINOR_AU1X00_UART0; + static UINT32 ekit1_major_tty1 = SYS_MAJOR_SERIAL_AU1X00; + static UINT32 ekit1_minor_tty1 = SERIAL_MINOR_AU1X00_UART3; + /* Baudrate conversion tables for UART divisor latch. * *************** *** 252,257 **** --- 267,297 ---- SERIAL_ILLEGAL /* 19: 921.600 baud */ }; + /* Au1x00 UART divisors for CPU freq of 396 MHz. */ + static t_SERIAL_baudrate_div serial_baudrate_div_Au1000 = + { + SERIAL_ILLEGAL, /* 0: not defined */ + SERIAL_ILLEGAL, /* 1: 75 baud */ + SERIAL_ILLEGAL, /* 2: 110 baud */ + SERIAL_ILLEGAL, /* 3: 150 baud */ + SERIAL_ILLEGAL, /* 4: 300 baud */ + SERIAL_ILLEGAL, /* 5: 600 baud */ + SERIAL_ILLEGAL, /* 6: 1.200 baud */ + SERIAL_ILLEGAL, /* 7: 1.800 baud */ + SERIAL_ILLEGAL, /* 8: 2.400 baud */ + SERIAL_ILLEGAL, /* 9: 4.800 baud */ + SERIAL_ILLEGAL, /* 10: 7.200 baud */ + 645, /* 11: 9.600 baud */ + SERIAL_ILLEGAL, /* 12: 14.400 baud */ + 322, /* 13: 19.200 baud */ + 161, /* 14: 38.400 baud */ + 107, /* 15: 57.600 baud */ + 54, /* 16: 115.200 baud */ + SERIAL_ILLEGAL, /* 17: 230.400 baud */ + SERIAL_ILLEGAL, /* 18: 460.800 baud */ + SERIAL_ILLEGAL /* 19: 921.600 baud */ + }; + /************************************************************************ * Static function prototypes *************** *** 484,489 **** --- 524,534 ---- } syscon_register_id_board( SYSCON_BOARD_TI16C550C_BASE0_ID, + #ifdef _ARCH_DEVDRV_EKIT1100 + /* E!Kit-1100 */ + NULL, NULL, + NULL, NULL ); + #else /* Atlas */ board_ti16c550c_base0_atlas_read, NULL, NULL, NULL, *************** *** 493,500 **** --- 538,551 ---- /* Malta */ board_ti16c550c_base0_malta_read, NULL, NULL, NULL ); + #endif /* #ifdef _ARCH_DEVDRV_EKIT1100 */ syscon_register_id_board( SYSCON_BOARD_TI16C550C_BASE1_ID, + #ifdef _ARCH_DEVDRV_EKIT1100 + /* E!Kit-1100 */ + NULL, NULL, + NULL, NULL ); + #else /* Atlas */ NULL, NULL, NULL, NULL, *************** *** 504,511 **** --- 555,568 ---- /* Malta */ board_ti16c550c_base1_malta_read, NULL, NULL, NULL ); + #endif /* #ifdef _ARCH_DEVDRV_EKIT1100 */ syscon_register_id_board( SYSCON_COM_TTY0_REG_SIZE_ID, + #ifdef _ARCH_DEVDRV_EKIT1100 + /* E!Kit-1100 */ + NULL, NULL, + NULL, NULL ); + #else /* Atlas (TI16550) */ syscon_uint8_read, &size32, NULL, NULL, *************** *** 515,522 **** --- 572,585 ---- /* Malta (TI16550) */ syscon_uint8_read, &size8, NULL, NULL ); + #endif /* #ifdef _ARCH_DEVDRV_EKIT1100 */ syscon_register_id_board( SYSCON_COM_TTY1_REG_SIZE_ID, + #ifdef _ARCH_DEVDRV_EKIT1100 + /* E!Kit-1100 */ + NULL, NULL, + NULL, NULL ); + #else /* Atlas (SAA9730) */ NULL, NULL, NULL, NULL, *************** *** 526,533 **** --- 589,602 ---- /* Malta (TI16550) */ board_reg_size1_malta_read, NULL, NULL, NULL ); + #endif /* #ifdef _ARCH_DEVDRV_EKIT1100 */ syscon_register_id_board( SYSCON_COM_TTY0_REG_SPACING_ID, + #ifdef _ARCH_DEVDRV_EKIT1100 + /* E!Kit-1100 */ + NULL, NULL, + NULL, NULL ); + #else /* Atlas (TI16550) */ syscon_uint8_read, &size64, NULL, NULL, *************** *** 537,544 **** --- 606,619 ---- /* Malta (TI16550) */ syscon_uint8_read, &size8, NULL, NULL ); + #endif /* #ifdef _ARCH_DEVDRV_EKIT1100 */ syscon_register_id_board( SYSCON_COM_TTY1_REG_SPACING_ID, + #ifdef _ARCH_DEVDRV_EKIT1100 + /* E!Kit-1100 */ + NULL, NULL, + NULL, NULL ); + #else /* Atlas (SAA9730) */ NULL, NULL, NULL, NULL, *************** *** 548,555 **** --- 623,636 ---- /* Malta (TI16550) */ board_reg_space1_malta_read, NULL, NULL, NULL ); + #endif /* #ifdef _ARCH_DEVDRV_EKIT1100 */ syscon_register_id_board( SYSCON_COM_TTY0_IC_IN_USE_ID, + #ifdef _ARCH_DEVDRV_EKIT1100 + /* E!Kit-1100 */ + NULL, NULL, + NULL, NULL ); + #else /* Atlas */ syscon_true_read, NULL, NULL, NULL, *************** *** 559,566 **** --- 640,653 ---- /* Malta */ syscon_true_read, NULL, NULL, NULL ); + #endif /* #ifdef _ARCH_DEVDRV_EKIT1100 */ syscon_register_id_board( SYSCON_COM_TTY1_IC_IN_USE_ID, + #ifdef _ARCH_DEVDRV_EKIT1100 + /* E!Kit-1100 */ + NULL, NULL, + NULL, NULL ); + #else /* Atlas */ syscon_true_read, NULL, NULL, NULL, *************** *** 570,577 **** --- 657,670 ---- /* Malta */ board_reg_ic1_malta_read, NULL, NULL, NULL ); + #endif /* #ifdef _ARCH_DEVDRV_EKIT1100 */ syscon_register_id_board( SYSCON_COM_TTY0_ADJUST_BREAK_ID, + #ifdef _ARCH_DEVDRV_EKIT1100 + /* E!Kit-1100 */ + NULL, NULL, + NULL, NULL ); + #else /* Atlas */ syscon_true_read, NULL, NULL, NULL, *************** *** 581,588 **** --- 674,687 ---- /* Malta */ syscon_true_read, NULL, NULL, NULL ); + #endif /* #ifdef _ARCH_DEVDRV_EKIT1100 */ syscon_register_id_board( SYSCON_COM_TTY1_ADJUST_BREAK_ID, + #ifdef _ARCH_DEVDRV_EKIT1100 + /* E!Kit-1100 */ + NULL, NULL, + NULL, NULL ); + #else /* Atlas */ syscon_false_read, NULL, NULL, NULL, *************** *** 592,599 **** --- 691,704 ---- /* Malta */ syscon_false_read, NULL, NULL, NULL ); + #endif /* #ifdef _ARCH_DEVDRV_EKIT1100 */ syscon_register_id_board( SYSCON_COM_TTY0_BIGEND_ID, + #ifdef _ARCH_DEVDRV_EKIT1100 + /* E!Kit-1100 */ + syscon_endian_big_read, NULL, + NULL, NULL ); + #else /* Atlas */ syscon_endian_big_read, NULL, NULL, NULL, *************** *** 603,610 **** --- 708,721 ---- /* Malta (PCI is always little endian) */ syscon_false_read, NULL, NULL, NULL ); + #endif /* #ifdef _ARCH_DEVDRV_EKIT1100 */ syscon_register_id_board( SYSCON_COM_TTY1_BIGEND_ID, + #ifdef _ARCH_DEVDRV_EKIT1100 + /* E!Kit-1100 */ + NULL, NULL, + NULL, NULL ); + #else /* Atlas (SAA9730 is PCI device and thus little endian) */ syscon_false_read, NULL, NULL, NULL, *************** *** 614,621 **** --- 725,738 ---- /* Malta (PCI is always little endian) */ board_bigend1_malta_read, NULL, NULL, NULL ); + #endif /* #ifdef _ARCH_DEVDRV_EKIT1100 */ syscon_register_id_board( SYSCON_COM_TTY0_INTLINE_ID, + #ifdef _ARCH_DEVDRV_EKIT1100 + /* E!Kit-1100 */ + NULL, NULL, + NULL, NULL ); + #else /* Atlas */ syscon_uint32_read, &intline_atlas_ti16550, NULL, NULL, *************** *** 625,632 **** --- 742,755 ---- /* Malta */ syscon_uint32_read, &intline_malta_ti16550_0, NULL, NULL ); + #endif /* #ifdef _ARCH_DEVDRV_EKIT1100 */ syscon_register_id_board( SYSCON_COM_TTY1_INTLINE_ID, + #ifdef _ARCH_DEVDRV_EKIT1100 + /* E!Kit-1100 */ + NULL, NULL, + NULL, NULL ); + #else /* Atlas */ syscon_uint32_read, &intline_atlas_saa9730, NULL, NULL, *************** *** 636,643 **** --- 759,772 ---- /* Malta */ board_intline1_malta_read, NULL, NULL, NULL ); + #endif /* #ifdef _ARCH_DEVDRV_EKIT1100 */ syscon_register_id_board( SYSCON_COM_TTY0_BAUDRATE_DIV_ID, + #ifdef _ARCH_DEVDRV_EKIT1100 + /* E!Kit-1100 */ + com_baudrate_div_read, (void *)&serial_baudrate_div_Au1000, + NULL, NULL ); + #else /* Atlas */ com_baudrate_div_read, (void *)&serial_baudrate_div_ti16550c, NULL, NULL, *************** *** 647,654 **** --- 776,789 ---- /* Malta */ com_baudrate_div_read, (void *)&serial_baudrate_div_smsc, NULL, NULL ); + #endif /* #ifdef _ARCH_DEVDRV_EKIT1100 */ syscon_register_id_board( SYSCON_COM_TTY1_BAUDRATE_DIV_ID, + #ifdef _ARCH_DEVDRV_EKIT1100 + /* E!Kit-1100 */ + com_baudrate_div_read, (void *)&serial_baudrate_div_Au1000, + NULL, NULL ); + #else /* Atlas */ com_baudrate_div_read, (void *)&serial_baudrate_div_saa9730, NULL, NULL, *************** *** 658,665 **** --- 793,806 ---- /* Malta */ board_baudrate1_div_malta_read, NULL, NULL, NULL ); + #endif /* #ifdef _ARCH_DEVDRV_EKIT1100 */ syscon_register_id_board( SYSCON_COM_TTY0_BAUDRATE_VERIFY_ID, + #ifdef _ARCH_DEVDRV_EKIT1100 + /* E!Kit-1100 */ + NULL, NULL, + com_baudrate_verify_write, (void *)&serial_baudrate_div_Au1000); + #else /* Atlas */ NULL, NULL, com_baudrate_verify_write, (void *)&serial_baudrate_div_ti16550c, *************** *** 669,676 **** --- 810,823 ---- /* Malta */ NULL, NULL, com_baudrate_verify_write, (void *)&serial_baudrate_div_smsc ); + #endif /* #ifdef _ARCH_DEVDRV_EKIT1100 */ syscon_register_id_board( SYSCON_COM_TTY1_BAUDRATE_VERIFY_ID, + #ifdef _ARCH_DEVDRV_EKIT1100 + /* E!Kit-1100 */ + NULL, NULL, + com_baudrate_verify_write, (void *)&serial_baudrate_div_Au1000); + #else /* Atlas */ NULL, NULL, com_baudrate_verify_write, (void *)&serial_baudrate_div_saa9730, *************** *** 680,687 **** --- 827,840 ---- /* Malta */ NULL, NULL, board_baudrate1_verify_malta_write, NULL ); + #endif /* #ifdef _ARCH_DEVDRV_EKIT1100 */ syscon_register_id_board( SYSCON_COM_TTY0_MAJOR, + #ifdef _ARCH_DEVDRV_EKIT1100 + /* E!Kit-1100 */ + syscon_uint32_read, &ekit1_major_tty0, + NULL, NULL ); + #else /* Atlas */ syscon_uint32_read, &atlas_major_tty0, NULL, NULL, *************** *** 691,698 **** --- 844,857 ---- /* Malta */ syscon_uint32_read, &malta_major_tty0, NULL, NULL ); + #endif /* #ifdef _ARCH_DEVDRV_EKIT1100 */ syscon_register_id_board( SYSCON_COM_TTY0_MINOR, + #ifdef _ARCH_DEVDRV_EKIT1100 + /* E!Kit-1100 */ + syscon_uint32_read, &ekit1_minor_tty0, + NULL, NULL ); + #else /* Atlas */ syscon_uint32_read, &atlas_minor_tty0, NULL, NULL, *************** *** 702,709 **** --- 861,874 ---- /* Malta */ syscon_uint32_read, &malta_minor_tty0, NULL, NULL ); + #endif /* #ifdef _ARCH_DEVDRV_EKIT1100 */ syscon_register_id_board( SYSCON_COM_TTY1_MAJOR, + #ifdef _ARCH_DEVDRV_EKIT1100 + /* E!Kit-1100 */ + syscon_uint32_read, &ekit1_major_tty1, + NULL, NULL ); + #else /* Atlas */ syscon_uint32_read, &atlas_major_tty1, NULL, NULL, *************** *** 713,720 **** --- 878,891 ---- /* Malta */ syscon_uint32_read, &malta_major_tty1, NULL, NULL ); + #endif /* #ifdef _ARCH_DEVDRV_EKIT1100 */ syscon_register_id_board( SYSCON_COM_TTY1_MINOR, + #ifdef _ARCH_DEVDRV_EKIT1100 + /* E!Kit-1100 */ + syscon_uint32_read, &ekit1_minor_tty1, + NULL, NULL ); + #else /* Atlas */ syscon_uint32_read, &atlas_minor_tty1, NULL, NULL, *************** *** 724,731 **** --- 895,908 ---- /* Malta */ syscon_uint32_read, &malta_minor_tty1, NULL, NULL ); + #endif /* #ifdef _ARCH_DEVDRV_EKIT1100 */ syscon_register_id_board( SYSCON_COM_TTY1_ON_TEXAS, + #ifdef _ARCH_DEVDRV_EKIT1100 + /* E!Kit-1100 */ + NULL, NULL, + NULL, NULL ); + #else /* Atlas */ NULL, NULL, NULL, NULL, *************** *** 735,740 **** --- 912,918 ---- /* Malta */ syscon_bool_read, (void *)&malta_tty1_on_texas, syscon_bool_write, (void *)&malta_tty1_on_texas ); + #endif /* #ifdef _ARCH_DEVDRV_EKIT1100 */ syscon_register_generic( SYSCON_BOARD_UART_COUNT_ID, syscon_uint8_read, (void *)&uart_count, diff -cNr yamon-sde6/bin/Makefile yamon-devdrv/bin/Makefile *** yamon-sde6/bin/Makefile Mon Jul 25 13:13:07 2005 --- yamon-devdrv/bin/Makefile Fri Jul 29 09:54:08 2005 *************** *** 148,160 **** # ******************************************************************** REVMAJ = 02 REVMIN = 06 # ******************************************************************** # Target prefix. # ******************************************************************** IMAGE_BASENAME = yamon ! IMAGENAME = $(IMAGE_BASENAME)-$(REVMAJ).$(REVMIN) ! RESET = reset-$(REVMAJ).$(REVMIN) # ******************************************************************** # Target filenames for little and big endian code. --- 148,162 ---- # ******************************************************************** REVMAJ = 02 REVMIN = 06 + COMPANY = devdrv + REVISION = 00 # ******************************************************************** # Target prefix. # ******************************************************************** IMAGE_BASENAME = yamon ! IMAGENAME = $(IMAGE_BASENAME)-$(REVMAJ).$(REVMIN)-$(COMPANY)-$(REVISION) ! RESET = reset-$(REVMAJ).$(REVMIN)-$(COMPANY)-$(REVISION) # ******************************************************************** # Target filenames for little and big endian code. *************** *** 381,388 **** W_OPTS = -Wimplicit -Wformat REV_OPTS = '-D_REVMAJ_="$(REVMAJ)"' '-D_REVMIN_="$(REVMIN)"' ! CC_OPTS = -mips2 -g -D_32_ -O2 -G0 -fno-builtin $(W_OPTS) $(REV_OPTS) $(INCLUDE) $(DEBUG) $(SIMULATE) $(BUILD_DEFS) -$(ENDIAN) -D$(ENDIAN) ifeq ($(BSS_OLD),0) CC_OPTS_A = $(CC_OPTS) $(AS_OPTS) -D_ASSEMBLER_ --- 383,391 ---- W_OPTS = -Wimplicit -Wformat REV_OPTS = '-D_REVMAJ_="$(REVMAJ)"' '-D_REVMIN_="$(REVMIN)"' + ARCH_OPTS = -D_ARCH_DEVDRV_EKIT1100 ! CC_OPTS = -mips2 -g -D_32_ -O2 -G0 -fno-builtin $(W_OPTS) $(REV_OPTS) $(INCLUDE) $(DEBUG) $(SIMULATE) $(BUILD_DEFS) -$(ENDIAN) -D$(ENDIAN) $(ARCH_OPTS) ifeq ($(BSS_OLD),0) CC_OPTS_A = $(CC_OPTS) $(AS_OPTS) -D_ASSEMBLER_ diff -cNr yamon-sde6/bin/link/link_eb.xn yamon-devdrv/bin/link/link_eb.xn *** yamon-sde6/bin/link/link_eb.xn Mon Jul 25 13:13:07 2005 --- yamon-devdrv/bin/link/link_eb.xn Thu Jul 21 19:16:53 2005 *************** *** 85,90 **** --- 85,91 ---- sead_platform.o (.text) init_cpu_s.o (.text) cache_cpu.o (.text) + ekit1100_platform.o (.text) . = ALIGN(8); _etext_init = ABSOLUTE(.); } = 0 diff -cNr yamon-sde6/bin/link/link_el.xn yamon-devdrv/bin/link/link_el.xn *** yamon-sde6/bin/link/link_el.xn Mon Jul 25 13:13:07 2005 --- yamon-devdrv/bin/link/link_el.xn Thu Jul 21 19:16:34 2005 *************** *** 85,90 **** --- 85,91 ---- sead_platform.o (.text) init_cpu_s.o (.text) cache_cpu.o (.text) + ekit1100_platform.o (.text) . = ALIGN(8); _etext_init = ABSOLUTE(.); } = 0 diff -cNr yamon-sde6/drivers/flash/flash_amd.c yamon-devdrv/drivers/flash/flash_amd.c *** yamon-sde6/drivers/flash/flash_amd.c Thu Jan 1 09:00:00 1970 --- yamon-devdrv/drivers/flash/flash_amd.c Tue Sep 27 16:32:15 2005 *************** *** 0 **** --- 1,1827 ---- + /************************************************************************ + * + * FLASH_AMD.C + * + * The 'FLASH_AMD' module implements the FLASH device driver + * interface to be used via 'IO' device driver services: + * + * 1) init device: configure and initialize FLASH driver + * 2) open device: not used + * 3) close device: not used + * 4) read device: not used + * 5) write device: write FLASH device + * 6) ctrl device: a) ERASE_SYSTEMFLASH + * b) ERASE_FILEFLASH + * + * + * + * ###################################################################### + * + * This program is largely copies by the FLASH_AMD(made by AMD) + * source files. + * + * Copyright 2005 Device Drivers Limited. + * Author: kawamoto@devdrv.co.jp + * + ************************************************************************/ + + /************************************************************************ + * Include files + ************************************************************************/ + + #include + #include + #include + #include + #include + #include + #include + #include + #include + #include + #include + #include + + /************************************************************************ + * Definitions + ************************************************************************/ + + /* FLASH-device, relative register address inside a block */ + #define FLASH_BLOCKSTATUS_OFS 0x0008 + + /* field: LOCK */ + #define FLASH_BLOCKSTATUS_LOCK_MSK 0x00010001 + + /* flash memory ID's */ + #define INTEL_MNFCR_CODE 0x0089 + #define AMD_DEV1_CODE 0x0014 + #define AMD_DEV2_CODE 0x0015 + + #define FLASH_QUERYQCHAR_OFS 0x0040 + #define FLASH_QUERYRCHAR_OFS 0x0044 + #define FLASH_QUERYYCHAR_OFS 0x0048 + + #define FLASH_QUERYQCHAR 0x00510051 + #define FLASH_QUERYRCHAR 0x00520052 + #define FLASH_QUERYYCHAR 0x00590059 + + /* status */ + #define FLASH_READY 0x0000 + #define FLASH_NOT_DETECTED 0x0001 + #define FLASH_BUSY 0x0002 + #define FLASH_ERROR 0x0003 + #define FLASH_TIMEOUT 0x0004 + #define FLASH_INVALID_SECTOR 0x0005 + #define FLASH_SECTOR_LOCKED 0x0006 + + /* Commands and masks, etc... */ + #define FLASH_STATUS_READY 0x00800080 + #define FLASH_STATUS_MASK 0x00FF00FF + #define FLASH_STATUS_OK 0x00800080 + #define FLASH_STATUS_ERASE 0x00600060 + #define FLASH_STATUS_LOCK 0x00020002 + #define FLASH_STATUS_LOW_VOLTAGE 0x00080008 + + #define FLASH_READ_COMMAND 0x00FF00FF + #define FLASH_ERASE_COMMAND 0x00200020 + #define FLASH_CONFIRM_COMMAND 0x00D000D0 + #define FLASH_CLEAR_STATUS_COMMAND 0x00500050 + #define FLASH_WRITE_WORD_COMMAND 0x00100010 + #define FLASH_WRITE_BUFFER_COMMAND 0x00E800E8 + #define FLASH_STATUS_COMMAND 0x00700070 + #define FLASH_QUERY_COMMAND 0x00980098 + #define FLASH_READ_ID_CODES_COMMAND 0x00900090 + #define FLASH_CLEAR_LOCK_COMMAND 0x00600060 + #define FLASH_LOCK_SECTOR 0x00010001 + + /* Timeout values */ + #define FLASH_TMOUT_100MS 100 + #define FLASH_TMOUT_250MS 250 + #define FLASH_TMOUT_500MS 500 + #define FLASH_TMOUT_1SEC 1000 + #define FLASH_TMOUT_2SEC 2000 + #define FLASH_TMOUT_2_5SEC 2500 + + /* Retry counts */ + #define FLASH_MAX_LOOPS 0xFFFFFFFF + #define FLASH_RETRY_5 5 + #define FLASH_RETRY_10 10 + #define FLASH_RETRY_20 20 + #define FLASH_RETRY_50 50 + + #define POLLING_MASK 0x00000080 + #define TIMING_LIMIT_MASK 0x00000020 + + #define ERASE_DATA 0xFFFFFFFF + + /* Identification tags for memory devices */ + typedef enum flash_device_id + { + FLASH_SYSTEMFLASH_DEVICE = 0, + FLASH_MONITORFLASH_DEVICE, + FLASH_FILEFLASH_DEVICE, + FLASH_BOOT_DEVICE, + FLASH_UNKNOWN_DEVICE + } t_flash_device_id ; + + /* union, to access bytes inside a word, independant of endianness */ + typedef union flash_access + { + volatile UINT32 d32 ; + volatile UINT8 d8[4] ; + } t_flash_access ; + + /************************************************************************ + * Macro Definitions + *************************************************************************/ + + #define WRITE_ENABLE SYSCON_write( SYSCON_BOARD_SYSTEMFLASH_WRITE_ENABLE_ID, \ + NULL, sizeof( UINT32 ) ); + + #define WRITE_DISABLE SYSCON_write( SYSCON_BOARD_SYSTEMFLASH_WRITE_DISABLE_ID, \ + NULL, sizeof( UINT32 ) ); + + /************************************************************************ + * Public variables + ************************************************************************/ + + + + /************************************************************************ + * Static variables + ************************************************************************/ + + static char* flash_error_string[] = + { + /* ERROR_FLASH_PROGRAM_ERROR */ "Flash device failure", + /* ERROR_FLASH_INVALID_ADDRESS */ "Invalid address", + /* ERROR_FLASH_INVALID_COMMAND */ "Internal ERROR: Invalid control command", + /* ERROR_FLASH_TIME_OUT */ "Internal ERROR: Flash device timed out during operation", + /* ERROR_FLASH_VERIFY_ERROR */ "Data verify error", + /* ERROR_FLASH_LOCKED */ "Some sectors are locked", + /* ERROR_FLASH_ERASE_ERROR */ "Sector has erase error", + /* ERROR_FLASH_LOW_VOLTAGE */ "Low programming voltage detected", + /* ERROR_FLASH_WRITE_PROTECTED */ "Flash is write protected", + /* ERROR_FLASH_FILE_FLASH_PROT */ "Environment FLASH is write protected", + /* ERROR_FLASH_FILE_FLASH_LOCK */ "Environment FLASH is lock-bit protected", + /* ERROR_FLASH_MONITOR_FLASH_LOCK */ "Some MONITOR FLASH sector(s) locked", + /* ERROR_FLASH_QRY_NOT_FOUND */ "CFI Query-ID string of FLASH not found", + /* ERROR_FLASH_BOOT_WRITE_PROTECTED */ "Write access to this area not allowed" + } ; + + static char* flash_error_hint_string[] = + { + /* ERROR_FLASH_PROGRAM_ERROR */ NULL, + /* ERROR_FLASH_INVALID_ADDRESS */ NULL, + /* ERROR_FLASH_INVALID_COMMAND */ NULL, + /* ERROR_FLASH_TIME_OUT */ NULL, + /* ERROR_FLASH_VERIFY_ERROR */ "Check flash has been erased before programming", + /* ERROR_FLASH_LOCKED */ "Unlock sector(s) before programming", + /* ERROR_FLASH_ERASE_ERROR */ NULL, + /* ERROR_FLASH_LOW_VOLTAGE */ NULL, + /* ERROR_FLASH_WRITE_PROTECTED */ "Disable write protection: Switch S1-3", + /* ERROR_FLASH_FILE_FLASH_PROT */ "Check programming addresses", + /* ERROR_FLASH_FILE_FLASH_LOCK */ "Disable 'clear lock-bit' protection: (MFWR-jumper) must be fitted", + /* ERROR_FLASH_MONITOR_FLASH_LOCK */ NULL, + /* ERROR_FLASH_QRY_NOT_FOUND */ NULL, + /* ERROR_FLASH_BOOT_WRITE_PROTECTED */ NULL + } ; + + static UINT32 flash_last_error ; + static char flash_diag_msg[160] ; + static char msg[160] ; + + + /* these variables are initialized at 'init' with the physical + address boundaries of: + + a) system FLASH + b) monitor FLASH + c) file FLASH. + + Following rule is to apply: + 'start' <= physical-device-address-space < 'end' + */ + + static UINT32 systemflash_phys_start ; + static UINT32 systemflash_phys_end ; + static UINT32 systemflash_block_size ; + static UINT32 systemflash_bank_count ; + static UINT32 systemflash_block_count ; + + static UINT32 monitorflash_phys_start ; + static UINT32 monitorflash_phys_end ; + static UINT32 monitorflash_block_size ; + static UINT32 monitorflash_bank_count ; + static UINT32 monitorflash_block_count ; + + static UINT32 fileflash_phys_start ; + static UINT32 fileflash_phys_end ; + static UINT32 fileflash_block_size ; + + static UINT32 boot_phys_start ; + static UINT32 boot_phys_end ; + + /************************************************************************ + * function prototypes + ************************************************************************/ + + + static + INT32 FLASH_AMD_init( + UINT32 major, /* IN: major device number */ + UINT32 minor, /* IN: minor device number */ + void *p_param ) ; /* INOUT: device parameter block */ + + static + INT32 FLASH_AMD_write( + UINT32 major, /* IN: major device number */ + UINT32 minor, /* IN: minor device number */ + t_FLASH_write_descriptor *p_param ) ; /* IN: write data */ + + static + INT32 FLASH_AMD_ctrl( + UINT32 major, /* IN: major device number */ + UINT32 minor, /* IN: minor device number */ + t_FLASH_ctrl_descriptor *p_param ); /* IN: write data */ + + static + bool FLASH_AMD_is_system_flash_write_protected( void ); + + static + bool FLASH_AMD_is_file_flash_write_protected( void ); + + static + bool FLASH_AMD_is_monitor_flash_write_protected( void ); + + static + t_flash_device_id FLASH_AMD_devicetype( UINT32 physadr ) ; + + static + INT32 FLASH_AMD_program_systemram( t_FLASH_write_descriptor *p_param ) ; + + static + INT32 FLASH_AMD_program_flash( t_FLASH_write_descriptor *p_param ) ; + + static + INT32 FLASH_AMD_set_systemflash_read( void ) ; + + static + INT32 FLASH_AMD_set_fileflash_read( void ) ; + + static + INT32 FLASH_AMD_set_monitorflash_read( void ) ; + + static + INT32 FLASH_AMD_erase_systemflash( void ) ; + + static + INT32 FLASH_AMD_erase_fileflash( void ) ; + + static + INT32 FLASH_AMD_erase_flasharea( t_FLASH_ctrl_descriptor *p_param ) ; + + static + INT32 FLASH_AMD_inquire_flasharea( t_FLASH_ctrl_descriptor *p_param ) ; + + static + INT32 FLASH_AMD_test_systemflash( void ) ; + + static + INT32 FLASH_AMD_test_fileflash( void ) ; + + static + INT32 FLASH_AMD_test_monitorflash( void ) ; + + static + INT32 FLASH_AMD_wait_ready(void *pw, long data ); + + static + INT32 FLASH_AMD_error_lookup( t_sys_error_string *p_param ) ; + + + /************************************************************************ + * Implementation : Public functions + ************************************************************************/ + + + /************************************************************************ + * + * FLASH_AMD_install + * Description : + * ------------- + * + * Installs the AMD FLASH device drivers services in + * the IO system at the reserved device slot, found in the + * 'sysdev.h' file, which defines all major device numbers. + * + * Note: + * This service is the only public declared interface function; all + * provided device driver services are static declared, but this + * function installs the function pointers in the io-system to + * enable the provided public driver services. + * + * Parameters : + * ------------ + * + * - + * + * + * Return values : + * --------------- + * + * 'OK'(=0) + * 'ERROR_IO_ILLEGAL_MAJOR': Illegal major device number + * 'ERROR_IO_NO_SPACE': Device slot already allocated + * + ************************************************************************/ + INT32 FLASH_AMD_install( void ) + { + t_sys_error_lookup_registration registration ; + + /* register lookup syserror */ + registration.prefix = SYSERROR_DOMAIN( ERROR_FLASH ) ; + registration.lookup = FLASH_AMD_error_lookup ; + SYSCON_write( SYSCON_ERROR_REGISTER_LOOKUP_ID, + ®istration, + sizeof( registration ) ); + + /* Revise - may want to update with SYS_MAJOR_FLASH_AMD + at this time too many places use SYS_MAJOR_FLASH_STRATA + so this should work */ + + /* pre-initialize local variables and install device services */ + IO_install( SYS_MAJOR_FLASH_STRATA, /* major device number */ + (t_io_service) FLASH_AMD_init, /* 'init' service */ + NULL, /* 'open' service na */ + NULL, /* 'close' service na */ + NULL, /* 'read' service */ + (t_io_service) FLASH_AMD_write, /* 'write' service */ + (t_io_service) FLASH_AMD_ctrl ) ; /* 'ctrl' service */ + + /* call our own 'init' service */ + return IO_init( SYS_MAJOR_FLASH_STRATA, 0, NULL); + } + + + + /************************************************************************ + * Implementation : Static functions + ************************************************************************/ + + /************************************************************************ + * + * FLASH_AMD_init + * Description : + * ------------- + * This service initializes the FLASH_AMD driver. + * + * + * Parameters : + * ------------ + * + * 'major', IN, major device number + * 'minor', IN, not used + * 'p_param', INOUT, not used + * + * + * Return values : + * --------------- + * + * 'OK'(=0) + * + * + * + ************************************************************************/ + static + INT32 FLASH_AMD_init( + UINT32 major, /* IN: major device number */ + UINT32 minor, /* IN: minor device number */ + void *p_param ) /* INOUT: device parameter block */ + { + int rcode ; + UINT32 *pt; + + /* initialize system profile: FLASH, address boundaries */ + + /* Update with latest boot phys end */ + + /* MIPS BOOT: */ + boot_phys_start = MIPS_RESET_VECTOR ; + boot_phys_end = 0x20000000 ; /* TBD: This size may change for future + board support packages */ + + /* SYSTEM FLASH: */ + /* get base for system flash */ + rcode = SYSCON_read( SYSCON_BOARD_SYSTEMFLASH_BASE_ID, + &systemflash_phys_start, + sizeof(systemflash_phys_start) ) ; + if (rcode != OK) + { + systemflash_phys_start = 0 ; + } + systemflash_phys_start = PHYS(systemflash_phys_start) ; + + /* get size for system flash */ + rcode = SYSCON_read( SYSCON_BOARD_SYSTEMFLASH_SIZE_ID, + &systemflash_phys_end, + sizeof(systemflash_phys_end) ) ; + if (rcode != OK) + { + systemflash_phys_end = 0 ; + } + systemflash_phys_end = systemflash_phys_start + systemflash_phys_end - 1; + + + /* MONITOR FLASH: */ + /* get base for monitor flash */ + rcode = SYSCON_read( SYSCON_BOARD_MONITORFLASH_BASE_ID, + &monitorflash_phys_start, + sizeof(monitorflash_phys_start) ) ; + if (rcode != OK) + { + monitorflash_phys_start = 0 ; + } + monitorflash_phys_start = PHYS(monitorflash_phys_start) ; + + /* get size for monitor flash */ + rcode = SYSCON_read( SYSCON_BOARD_MONITORFLASH_SIZE_ID, + &monitorflash_phys_end, + sizeof(monitorflash_phys_end) ) ; + if (rcode != OK) + { + monitorflash_phys_end = 0 ; + } + monitorflash_phys_end = monitorflash_phys_start + monitorflash_phys_end - 1; + + /* FILE FLASH: */ + /* get base for file flash */ + rcode = SYSCON_read( SYSCON_BOARD_FILEFLASH_BASE_ID, + &fileflash_phys_start, + sizeof(fileflash_phys_start) ) ; + if (rcode != OK) + { + fileflash_phys_start = 0 ; + } + fileflash_phys_start = PHYS(fileflash_phys_start) ; + + /* get size for file flash */ + rcode = SYSCON_read( SYSCON_BOARD_FILEFLASH_SIZE_ID, + &fileflash_phys_end, + sizeof(fileflash_phys_end) ) ; + if (rcode != OK) + { + fileflash_phys_end = 0 ; + } + fileflash_phys_end = fileflash_phys_start + fileflash_phys_end - 1; + + + /* get system flash sector size */ + rcode = SYSCON_read( SYSCON_BOARD_SYSTEMFLASH_SECTORSIZE_ID, + &systemflash_block_size, + sizeof(systemflash_block_size) ) ; + + if (rcode != OK) + { + systemflash_block_size = 0 ; + } + + /* get monitor flash sector size */ + rcode = SYSCON_read( SYSCON_BOARD_MONITORFLASH_SECTORSIZE_ID, + &monitorflash_block_size, + sizeof(monitorflash_block_size) ) ; + + if (rcode != OK) + { + monitorflash_block_size = 0 ; + } + + /* get file flash sector size */ + rcode = SYSCON_read( SYSCON_BOARD_FILEFLASH_SECTORSIZE_ID, + &fileflash_block_size, + sizeof(fileflash_block_size) ) ; + + if (rcode != OK) + { + fileflash_block_size = 0 ; + } + + /* get system flash bank count */ + rcode = SYSCON_read( SYSCON_BOARD_SYSTEMFLASH_BANKCOUNT_ID, + &systemflash_bank_count, + sizeof(systemflash_bank_count) ) ; + if (rcode != OK) + { + systemflash_bank_count = 0 ; + } + + /* get system flash block count */ + rcode = SYSCON_read( SYSCON_BOARD_SYSTEMFLASH_BLOCKCOUNT_ID, + &systemflash_block_count, + sizeof(systemflash_block_count) ) ; + if (rcode != OK) + { + systemflash_block_count = 0 ; + } + + pt = (UINT32*) KSEG1(fileflash_phys_start); + + + + return( OK ) ; + } + + + /************************************************************************ + * + * FLASH_AMD_write + * Description : + * ------------- + * This service writes data into a specified address location, which + * can be in either SYSTEM-FLASH or FILE-FLASH space. Default is RAM. + * + * + * Parameters : + * ------------ + * + * 'major', IN, major device number + * 'minor', IN, minor device number for multi device drivers + * 'p_param', IN, variable of type, t_FLASH_write_descriptor. + * + * + * Return values : + * --------------- + * + * 'OK' = 0x00: data has been stored + * ERROR_FLASH_PROGRAM_ERROR Flash device failure + * ERROR_FLASH_INVALID_ADDRESS, Physical address not impl. + * + * + ************************************************************************/ + static + INT32 FLASH_AMD_write( + UINT32 major, /* IN: major device number */ + UINT32 minor, /* IN: minor device number */ + t_FLASH_write_descriptor *p_param ) /* IN: write data */ + { + int rcode = OK ; + + + /* set to default */ + flash_diag_msg[0] = 0 ; + + switch (FLASH_AMD_devicetype(PHYS(p_param->adr))) + { + case FLASH_SYSTEMFLASH_DEVICE: + /* program system FLASH */ + if ( FLASH_AMD_is_system_flash_write_protected() ) + { + rcode = ERROR_FLASH_WRITE_PROTECTED ; + } + else + { + rcode = FLASH_AMD_program_flash( p_param ) ; + + /* set system flash banks in read array mode */ + FLASH_AMD_set_systemflash_read(); + } + break ; + + case FLASH_FILEFLASH_DEVICE: + + + /* Reject user to program FILE FLASH */ + memset( flash_diag_msg, 0, sizeof(flash_diag_msg) ) ; + sprintf( flash_diag_msg, "Environment FLASH: map = (0x%08x,0x%08x), user = 0x%08x", + (UINT32) fileflash_phys_start, + (UINT32) fileflash_phys_end, + (UINT32) PHYS(p_param->adr) ) ; + rcode = ERROR_FLASH_FILE_FLASH_PROT ; + + break ; + + + case FLASH_MONITORFLASH_DEVICE: + /* program monitor FLASH */ + rcode = FLASH_AMD_program_flash( p_param ) ; + + /* set monitor flash in read array mode */ + FLASH_AMD_set_monitorflash_read(); + break ; + + case FLASH_BOOT_DEVICE: + /* Boot device */ + memset( flash_diag_msg, 0, sizeof(flash_diag_msg) ) ; + sprintf( flash_diag_msg, "MIPS boot media: map = (0x%08x,0x%08x), user = 0x%08x", + (UINT32) boot_phys_start, + (UINT32) boot_phys_end, + (UINT32) PHYS(p_param->adr) ) ; + rcode = ERROR_FLASH_BOOT_WRITE_PROTECTED ; + break ; + + default: + /* program any RAM */ + rcode = FLASH_AMD_program_systemram( p_param ) ; + break ; + } + flash_last_error = rcode ; + return( rcode ) ; + } + + + /************************************************************************ + * + * FLASH_AMD_ctrl + * Description : + * ------------- + * This service comprise following specific FLASH services: + * 1) 'ERASE_SYSTEMFLASH' + * 2) 'ERASE_FILEFLASH' + * 3) 'FLASH_CTRL_ERASE_FLASH_AREA' + * 4) 'FLASH_CTRL_INQUIRE_FLASH_AREA' + * 5) 'FLASH_CTRL_TEST_SYSTEMFLASH' + * + * + * Parameters : + * ------------ + * + * 'major', IN, major device number + * 'minor', IN, minor device number for multi device drivers + * 'p_param', IN, variable of type, t_FLASH_ctrl_descriptor. + * + * + * Return values : + * --------------- + * + * 'OK' = 0x00: FLASH service completed successfully + * ERROR_FLASH_PROGRAM_ERROR Flash device failure + * + * + ************************************************************************/ + static + INT32 FLASH_AMD_ctrl( + UINT32 major, /* IN: major device number */ + UINT32 minor, /* IN: minor device number */ + t_FLASH_ctrl_descriptor *p_param ) /* IN: write data */ + { + int rcode = OK ; + UINT32 *pt; + + /* set to default */ + flash_diag_msg[0] = 0 ; + + switch(p_param->command) + { + case FLASH_CTRL_ERASE_SYSTEMFLASH: + if ( FLASH_AMD_is_system_flash_write_protected() ) + { + rcode = ERROR_FLASH_WRITE_PROTECTED ; + } + else + { + rcode = FLASH_AMD_erase_systemflash() ; + } + break ; + + case FLASH_CTRL_ERASE_FILEFLASH: + + #ifdef PROMICE + + /* added to emulate flash */ + + pt = (UINT32*) KSEG1(fileflash_phys_start); + + /*PBUpdate added so SRAM could fake flash */ + + while(KSEG1((UINT32)pt) < KSEG1(fileflash_phys_end)) + { + REG32(pt) = 0xffffffff; + pt++; + } + #else + + rcode = FLASH_AMD_erase_fileflash() ; + + #endif /*PROMICE*/ + + break ; + + case FLASH_CTRL_ERASE_FLASH_AREA: + rcode = FLASH_AMD_erase_flasharea(p_param) ; + break ; + + case FLASH_CTRL_INQUIRE_FLASH_AREA: + rcode = FLASH_AMD_inquire_flasharea(p_param) ; + break ; + + case FLASH_CTRL_TEST_SYSTEMFLASH: + rcode = FLASH_AMD_test_systemflash() ; + if (rcode == OK) + { + rcode = FLASH_AMD_test_fileflash() ; + } + break ; + + case FLASH_CTRL_WRITE_FILEFLASH: + /* program file FLASH */ + + #ifdef PROMICE + + rcode = FLASH_AMD_program_systemram( p_param->wr_param ); + #else + + rcode = FLASH_AMD_program_flash( p_param->wr_param ); + if (rcode == ERROR_FLASH_LOCKED) + { + if ( FLASH_AMD_is_file_flash_write_protected() ) + { + rcode = ERROR_FLASH_FILE_FLASH_LOCK ; + } + } + + /* set file flash in read array mode */ + FLASH_AMD_set_fileflash_read(); + + #endif /*PROMICE*/ + + break ; + + case FLASH_CTRL_TEST_MONITORFLASH: + rcode = FLASH_AMD_test_monitorflash() ; + break ; + + default: + printf("invalid flash command...\n"); + rcode = ERROR_FLASH_INVALID_COMMAND ; + break ; + } + flash_last_error = rcode ; + return( rcode ) ; + } + + + /************************************************************************ + * Local helper functions + ************************************************************************/ + + /************************************************************************ + * + * FLASH_AMD_devicetype + * Description : + * ------------- + * Derive the memory device type from 'physical address' + * + * + * Parameters : + * ------------ + * + * 'physadr': physical address inside a 512 MByte space + * + * + * Return values : + * --------------- + * + * t_flash_device_id: memory device type detected. + * + * + ************************************************************************/ + static + t_flash_device_id FLASH_AMD_devicetype( UINT32 physadr ) + { + /* check for system FLASH */ + if ((systemflash_phys_start <= physadr) && (physadr <= systemflash_phys_end)) + { + return(FLASH_SYSTEMFLASH_DEVICE) ; + } + + /* check for BOOT */ + /* if (( boot_phys_start <= physadr) && (physadr <= boot_phys_end )) + { + return(FLASH_BOOT_DEVICE) ; + } + */ + /* check for monitor FLASH */ + if ((monitorflash_phys_start <= physadr) && (physadr <= monitorflash_phys_end)) + { + return(FLASH_MONITORFLASH_DEVICE) ; + } + + /* check for file FLASH */ + if ((fileflash_phys_start <= physadr) && (physadr <= fileflash_phys_end)) + { + return(FLASH_FILEFLASH_DEVICE) ; + } + + + + /* device not known */ + return(FLASH_UNKNOWN_DEVICE) ; + } + + + /************************************************************************ + * + * FLASH_AMD_program_systemram + * Description : + * ------------- + * Programs (store data) in the system RAM device. + * + * + * Parameters : + * ------------ + * + * 'p_param', IN, variable of type, t_FLASH_write_descriptor. + * + * + * Return values : + * --------------- + * + * 'OK' = 0x00: Data stored in system RAM + * + * + ************************************************************************/ + static + INT32 FLASH_AMD_program_systemram( t_FLASH_write_descriptor *p_param ) + { + int i, len ; + UINT8 *psrc ; + UINT8 *pdst ; + + /* set addresses */ + psrc = (UINT8*) p_param->buffer ; + pdst = (UINT8*) KSEG1(p_param->adr) ; + len = p_param->length ; + + /* call our speedy memcpy */ + memcpy( pdst, psrc, len ) ; + + return(OK) ; + } + + /************************************************************************ + * + * FLASH_AMD_program_flash + * Description : + * ------------- + * Programs a Intel 28Fxxx-compliant flash device. + * + * + * Parameters : + * ------------ + * + * 'p_param', IN, variable of type, t_FLASH_write_descriptor. + * + * + * Return values : + * --------------- + * + * 'OK' = 0x00: FLASH programmed succesfully + * ERROR_FLASH_PROGRAM_ERROR Flash device failure + * + * + ************************************************************************/ + void dumphex(short *p, int len) + { + int i; + + i = 0; + while( i < len ) + { + if( (i % 16) == 0 ) + printf("\n%08x: ",(UINT32)&p[i/2]); + printf("%04x ",p[i/2] & 0x00ffff); + i += 2; + } + printf("\n"); + } + + static + INT32 FLASH_AMD_program_flash( t_FLASH_write_descriptor *p_param ) + { + int rcode = OK; + int i, len; + volatile short *psrc; + volatile short *pdst; + volatile short *flash; + + /* convert addresses to kseg1 */ + psrc = (short *)p_param->buffer; + pdst = (short *)KSEG1((UINT32)p_param->adr); + len = p_param->length; + flash = (short *)((long)pdst & 0xFFC00000); + + /* check any special case */ + if (len <= 0) + { + printf("len <= 0\n"); + return(OK); + } + + if( ((UINT32)psrc & 0x00000001) || ((UINT32)pdst & 0x00000001)) + { + memset( flash_diag_msg, 0, sizeof(flash_diag_msg) ); + sprintf(flash_diag_msg, " alignment error (halfword) src = %08x, dst = %08x",(UINT32)psrc,(UINT32)pdst); + return(ERROR_FLASH_VERIFY_ERROR); + } + + /* both source and destination must be halfword aligned */ + + /* program word by word */ + for ( i = 0; i < len; i += 2) + { + /* program one halfword */ + /* These are the commands to write a halfword into AMD flash */ + + flash[0x555] = 0x00AA; + flash[0x2AA] = 0x0055; + flash[0x555] = 0x00A0; + *pdst = *psrc; + + /* await completion */ + rcode = FLASH_AMD_wait_ready( (void *)pdst, *psrc); + if (rcode) + { + printf(" programming error.\n"); + return(rcode); + } + + /* Verify programmed word */ + + if ( *pdst != *psrc ) + { + memset( flash_diag_msg, 0, sizeof(flash_diag_msg) ) ; + sprintf( flash_diag_msg, "Data check read: (0x%08x)=0x%04x, Data written: 0x%04x", + (UINT32)pdst, *pdst & 0x0ffff, *psrc & 0x0ffff) ; + return(ERROR_FLASH_VERIFY_ERROR) ; + } + + /* next destination and source word */ + ++pdst; + ++psrc; + } + return( rcode ) ; + } + + /************************************************************************ + * + * FLASH_AMD_set_systemflash_read + * Description : + * ------------- + * Set system flash device in read mode. + * + * + * Parameters : + * ------------ + * + * - + * + * + * Return values : + * --------------- + * + * 'OK' = 0x00: System FLASH set to read mode + * ERROR_FLASH_PROGRAM_ERROR Flash device failure + * + * + ************************************************************************/ + static + INT32 FLASH_AMD_set_systemflash_read( void ) + { + int rcode ; + UINT32 bank ; + volatile UINT32 *pw ; + + /* The address is actually a don't care but you need to put something */ + + pw = (UINT32*) KSEG1(systemflash_phys_start) ; + + /* The first reset will take us out of any command modes */ + + REG32(pw) = 0x00f000f0; + + /* The second reset will reset all banks in flash to read mode */ + + REG32(pw) = 0x00f000f0; + + return( OK ) ; + } + + + /************************************************************************ + * + * FLASH_AMD_set_fileflash_read + * Description : + * ------------- + * Set file flash device in read mode. + * + * + * Parameters : + * ------------ + * + * - + * + * + * Return values : + * --------------- + * + * 'OK' = 0x00: File FLASH set to read mode + * ERROR_FLASH_PROGRAM_ERROR Flash device failure + * + * + ************************************************************************/ + static + INT32 FLASH_AMD_set_fileflash_read( void ) + { + int rcode ; + UINT32 bank ; + volatile UINT32 *pw ; + + pw = (UINT32*) KSEG1(fileflash_phys_start) ; + + /* The first reset will take us out of any command modes */ + + REG32(pw) = 0x00f000f0; + + /* The second reset will reset all banks in flash to read mode */ + + REG32(pw) = 0x00f000f0; + + + return( OK ) ; + } + + + /************************************************************************ + * + * FLASH_AMD_set_monitorflash_read + * Description : + * ------------- + * Set monitor flash device in read mode. + * + * + * Parameters : + * ------------ + * + * - + * + * + * Return values : + * --------------- + * + * 'OK' = 0x00: File FLASH set to read mode + * ERROR_FLASH_PROGRAM_ERROR Flash device failure + * + * + ************************************************************************/ + static + INT32 FLASH_AMD_set_monitorflash_read( void ) + { + int rcode ; + UINT32 bank ; + volatile UINT32 *pw ; + + pw = (UINT32*) KSEG1(monitorflash_phys_start) ; + + /* The first reset will take us out of any command modes */ + + *pw = 0x00f000f0; + + /* The second reset will reset all banks in flash to read mode */ + + *pw = 0x00f000f0; + + return( OK ) ; + } + + /************************************************************************ + * + * erase_AMD_flash + * Description : + * ------------- + * Erase AMD flash. + * + * + * Parameters : + * ------------ + * + * - + * + * + * Return values : + * --------------- + * + * 'OK' = 0x00: FLASH erased succesfully + * + * + ************************************************************************/ + INT32 erase_AMD_flash(UINT32 startaddr, UINT32 endaddr) + { + int rcode = ERROR_FLASH_INVALID_ADDRESS; + volatile short *fptr = (volatile short *)KSEG1(startaddr); + #define FL_CMD(c) (c) + + endaddr = KSEG1(endaddr); + startaddr = KSEG1(startaddr); + + while( (UINT32)fptr < endaddr ) + { + fptr[0x555] = FL_CMD(0xaa); + fptr[0x2AA] = FL_CMD(0x55); + fptr[0x555] = FL_CMD(0x80); + fptr[0x555] = FL_CMD(0xaa); + fptr[0x2AA] = FL_CMD(0x55); + fptr[0] = FL_CMD(0x30); + + /* await completion */ + rcode = FLASH_AMD_wait_ready( (void *)fptr, ERASE_DATA); + if (rcode != OK) + { + printf("erase error.\n"); + break ; + } + + (long)fptr += systemflash_block_size; + } + return rcode; + } + + + /************************************************************************ + * + * FLASH_AMD_erase_systemflash + * Description : + * ------------- + * Erase complete system flash. + * + * + * Parameters : + * ------------ + * + * - + * + * Return values : + * --------------- + * + * 'OK' = 0x00: System FLASH erased succesfully + * ERROR_FLASH_PROGRAM_ERROR Flash device failure + * + * + ************************************************************************/ + static + INT32 FLASH_AMD_erase_systemflash( void ) + { + return erase_AMD_flash(systemflash_phys_start, systemflash_phys_end); + } + + /************************************************************************ + * + * FLASH_AMD_erase_fileflash + * Description : + * ------------- + * Erase file flash, which is the last block (in each FLASH device) + * of the monitor flash. + * + * + * Parameters : + * ------------ + * + * - + * + * Return values : + * --------------- + * + * 'OK' = 0x00: File FLASH erased succesfully + * ERROR_FLASH_PROGRAM_ERROR Flash device failure + * + * + ************************************************************************/ + static + INT32 FLASH_AMD_erase_fileflash( void ) + { + return erase_AMD_flash(fileflash_phys_start, fileflash_phys_end); + } + + /************************************************************************ + * + * FLASH_AMD_erase_flasharea + * Description : + * ------------- + * Erase flash area; i.e. the driver erases the flash blocks inside + * the specified memory area. + * + * + * Parameters : + * ------------ + * + * 'p_param', IN, variable of type, t_FLASH_ctrl_descriptor. + * + * + * Return values : + * --------------- + * + * 'OK' = 0x00: FLASH erased succesfully + * ERROR_FLASH_PROGRAM_ERROR Flash device failure + * ERROR_FLASH_INVALID_ADDRESS Address area not inside FLASH + * devices + * + * + ************************************************************************/ + static + INT32 FLASH_AMD_erase_flasharea( t_FLASH_ctrl_descriptor *p_param ) + { + int rcode = OK ; + long startaddr, endaddr; + + /* calculate committed FLASH area */ + startaddr = KSEG1(p_param->user_physadr); + endaddr = KSEG1(p_param->user_physadr) + p_param->user_length - 1; + return erase_AMD_flash(startaddr,endaddr); + } + + + /************************************************************************ + * + * FLASH_AMD_inquire_flasharea + * Description : + * ------------- + * Inquire flash area; i.e. the driver calculates the effective flash + * block area covering the specified memory area. + * + * + * Parameters : + * ------------ + * + * 'p_param', IN, variable of type, t_FLASH_ctrl_descriptor. + * + * + * Return values : + * --------------- + * + * 'OK' = 0x00: Area specified inside valid + * FLASH device area + * ERROR_FLASH_INVALID_ADDRESS Address area not inside FLASH + * devices + * + * + ************************************************************************/ + static + INT32 FLASH_AMD_inquire_flasharea( t_FLASH_ctrl_descriptor *p_param ) + { + UINT32 blocksize, start, end ; + + switch (FLASH_AMD_devicetype(p_param->user_physadr)) + { + case FLASH_SYSTEMFLASH_DEVICE: + /* system FLASH */ + + /* validate upper boundary */ + if ( FLASH_AMD_devicetype( p_param->user_physadr + + p_param->user_length - 1 ) + != FLASH_SYSTEMFLASH_DEVICE ) + { + return( ERROR_FLASH_INVALID_ADDRESS ) ; + } + + blocksize = systemflash_block_size ; + break ; + + case FLASH_FILEFLASH_DEVICE: + /* Reject programming of FILE FLASH */ + memset( flash_diag_msg, 0, sizeof(flash_diag_msg) ) ; + sprintf( flash_diag_msg, "Environment FLASH: map = (0x%08x,0x%08x), user = 0x%08x", + (UINT32) fileflash_phys_start, + (UINT32) fileflash_phys_end, + (UINT32) PHYS(p_param->user_physadr) ) ; + return( ERROR_FLASH_FILE_FLASH_PROT ) ; + break ; + + case FLASH_MONITORFLASH_DEVICE: + /* Monitor FLASH */ + /* validate upper boundary */ + if ( FLASH_AMD_devicetype( p_param->user_physadr + + p_param->user_length - 1 ) + != FLASH_MONITORFLASH_DEVICE ) + { + return( ERROR_FLASH_INVALID_ADDRESS ) ; + } + + blocksize = monitorflash_block_size ; + break ; + + case FLASH_BOOT_DEVICE: + /* Boot device */ + memset( flash_diag_msg, 0, sizeof(flash_diag_msg) ) ; + sprintf( flash_diag_msg, "MIPS boot media: map = (0x%08x,0x%08x), user = 0x%08x", + (UINT32) boot_phys_start, + (UINT32) boot_phys_end, + (UINT32) PHYS(p_param->user_physadr) ) ; + return( ERROR_FLASH_BOOT_WRITE_PROTECTED ) ; + break ; + + default: + return( ERROR_FLASH_INVALID_ADDRESS ) ; + break ; + } + + /* calculate committed FLASH area */ + start = (KSEG1(p_param->user_physadr)/blocksize) * blocksize ; + end = ((((KSEG1(p_param->user_physadr) + + p_param->user_length)/blocksize)) * blocksize) - 1 ; + if ( ((KSEG1(p_param->user_physadr)+p_param->user_length) % blocksize) != 0) + { + end = end + blocksize ; + } + + /* return committed area to user */ + p_param->driver_physadr = PHYS(start) ; + p_param->driver_length = (end - start) + 1 ; + + return( OK ) ; + } + + + /************************************************************************ + * + * FLASH_AMD_test_systemflash + * Description : + * ------------- + * Test complete file flash (just one block) + * + * + * Parameters : + * ------------ + * + * - + * + * Return values : + * --------------- + * + * 'OK' = 0x00: System FLASH OK + * ERROR_FLASH_LOCKED Some sector(s) locked + * ERROR_FLASH_ERASE_ERROR Some sector(s) have erase error + * + * + ************************************************************************/ + static + INT32 FLASH_AMD_test_systemflash( void ) + { + int rcode = OK ; + UINT32 block, bank ; + volatile UINT32 *pw ; + + return OK; // *** kludge *** + + pw = (UINT32 *) 0xbf800000; + + /* issue 'QUERY' command */ + REG32(pw + 0x55) = 0x00980098; + + #ifdef FLASH_DEBUG + sprintf( msg, "\n\r FLASH_AMD_test_systemflash: Adr= 0x%08x, Sta= 0x%08x\n\r", + (UINT32)pw, REG32( ((UINT32)pw+FLASH_BLOCKSTATUS_OFS) ) ) ; + PUTS( DEFAULT_PORT, msg ) ; + #endif + + /* Verify 'Q' char of the Query-unique ASCII string, part of CFI spec. */ + if ( REG32(pw + 0x10) != FLASH_QUERYQCHAR ) + { + memset( flash_diag_msg, 0, sizeof(flash_diag_msg) ) ; + sprintf( flash_diag_msg, "Adr= %08x, (Adr)= %08x",(UINT32)pw+FLASH_QUERYQCHAR_OFS, + REG32(((UINT32)pw+FLASH_QUERYQCHAR_OFS)) ) ; + rcode = ERROR_FLASH_QRY_NOT_FOUND ; + } + + /* Verify 'R' char of the Query-unique ASCII string, part of CFI spec. */ + if ( REG32(pw + 0x11) != FLASH_QUERYRCHAR ) + { + memset( flash_diag_msg, 0, sizeof(flash_diag_msg) ) ; + sprintf( flash_diag_msg, "Adr= %08x, (Adr)= %08x",(UINT32)pw+FLASH_QUERYRCHAR_OFS, + REG32(((UINT32)pw+FLASH_QUERYRCHAR_OFS)) ) ; + rcode = ERROR_FLASH_QRY_NOT_FOUND ; + } + + /* Verify 'Y' char of the Query-unique ASCII string, part of CFI spec. */ + if ( REG32(pw + 0x12) != FLASH_QUERYYCHAR ) + { + memset( flash_diag_msg, 0, sizeof(flash_diag_msg) ) ; + sprintf( flash_diag_msg, "Adr= %08x, (Adr)= %08x",(UINT32)pw+FLASH_QUERYYCHAR_OFS, + REG32(((UINT32)pw+FLASH_QUERYYCHAR_OFS)) ) ; + rcode = ERROR_FLASH_QRY_NOT_FOUND ; + } + + /* Issue Reset Command to return to read mode */ + + REG32(pw) = 0x00f000f0; + + return( rcode ) ; + } + + + /************************************************************************ + * + * FLASH_AMD_test_fileflash + * Description : + * ------------- + * Test complete file flash. + * + * + * Parameters : + * ------------ + * + * - + * + * Return values : + * --------------- + * + * 'OK' = 0x00: System FLASH OK + * ERROR_FLASH_LOCKED Some sector(s) locked + * ERROR_FLASH_ERASE_ERROR Some sector(s) have erase error + * + * + ************************************************************************/ + static + INT32 FLASH_AMD_test_fileflash( void ) + { + int rcode = OK ; + volatile UINT32 *pw ; + + return OK; // *** kludge *** + + pw = (UINT32 *)0xbf800000; + + /* issue 'QUERY' command */ + REG32(pw + 0x55) = 0x00980098; + + #ifdef FLASH_DEBUG + sprintf( msg, "\n\r FLASH_AMD_test_systemflash: Adr= 0x%08x, Sta= 0x%08x\n\r", + (UINT32)pw, REG32( ((UINT32)pw+FLASH_BLOCKSTATUS_OFS) ) ) ; + PUTS( DEFAULT_PORT, msg ) ; + #endif + + /* Verify 'Q' char of the Query-unique ASCII string, part of CFI spec. */ + if ( REG32(pw + 0x10) != FLASH_QUERYQCHAR ) + { + memset( flash_diag_msg, 0, sizeof(flash_diag_msg) ) ; + sprintf( flash_diag_msg, "Adr= %08x, (Adr)= %08x",(UINT32)pw+FLASH_QUERYQCHAR_OFS, + REG32(((UINT32)pw+FLASH_QUERYQCHAR_OFS)) ) ; + rcode = ERROR_FLASH_QRY_NOT_FOUND ; + + } + + /* Verify 'R' char of the Query-unique ASCII string, part of CFI spec. */ + if ( REG32(pw + 0x11) != FLASH_QUERYRCHAR ) + { + memset( flash_diag_msg, 0, sizeof(flash_diag_msg) ) ; + sprintf( flash_diag_msg, "Adr= %08x, (Adr)= %08x",(UINT32)pw+FLASH_QUERYRCHAR_OFS, + REG32(((UINT32)pw+FLASH_QUERYRCHAR_OFS)) ) ; + rcode = ERROR_FLASH_QRY_NOT_FOUND ; + + } + + /* Verify 'Y' char of the Query-unique ASCII string, part of CFI spec. */ + if ( REG32(pw + 0x12) != FLASH_QUERYYCHAR ) + { + memset( flash_diag_msg, 0, sizeof(flash_diag_msg) ) ; + sprintf( flash_diag_msg, "Adr= %08x, (Adr)= %08x",(UINT32)pw+FLASH_QUERYYCHAR_OFS, + REG32(((UINT32)pw+FLASH_QUERYYCHAR_OFS)) ) ; + rcode = ERROR_FLASH_QRY_NOT_FOUND ; + + } + + /* Issue Reset Command to return to read mode */ + + REG32(pw) = 0x00f000f0; + + return( rcode ) ; + } + + + /************************************************************************ + * + * FLASH_AMD_test_monitorflash + * Description : + * ------------- + * Test and set lock bits of complete monitor flash (including file flash) + * The lower 1 Mbytes hold YAMON and are locked (write protected) + * The upper 3 Mbytes are unlocked. + * + * + * Parameters : + * ------------ + * + * - + * + * Return values : + * --------------- + * + * 'OK' = 0x00: System FLASH OK + * ERROR_FLASH_LOCKED Some sector(s) locked + * ERROR_FLASH_ERASE_ERROR Some sector(s) have erase error + * + ************************************************************************/ + static + INT32 FLASH_AMD_test_monitorflash( void ) + { + int rcode = OK ; + volatile UINT32 *pw ; + UINT32 pw_lock_end; + UINT32 pw_unlock_end; + + return OK; // *** kludge *** + + pw = (UINT32 *) 0xbf800000; + + + /* issue 'QUERY' command */ + REG32(pw + 0x55) = 0x00980098; + + #ifdef FLASH_DEBUG + sprintf( msg, "\n\r FLASH_AMD_test_systemflash: Adr= 0x%08x, Sta= 0x%08x\n\r", + (UINT32)pw, REG32( ((UINT32)pw+FLASH_BLOCKSTATUS_OFS) ) ) ; + PUTS( DEFAULT_PORT, msg ) ; + #endif + + /* Verify 'Q' char of the Query-unique ASCII string, part of CFI spec. */ + if ( REG32(pw + 0x10) != FLASH_QUERYQCHAR ) + { + memset( flash_diag_msg, 0, sizeof(flash_diag_msg) ) ; + sprintf( flash_diag_msg, "Adr= %08x, (Adr)= %08x",(UINT32)pw+FLASH_QUERYQCHAR_OFS, + REG32(((UINT32)pw+FLASH_QUERYQCHAR_OFS)) ) ; + rcode = ERROR_FLASH_QRY_NOT_FOUND ; + + } + + /* Verify 'R' char of the Query-unique ASCII string, part of CFI spec. */ + if ( REG32(pw + 0x11) != FLASH_QUERYRCHAR ) + { + memset( flash_diag_msg, 0, sizeof(flash_diag_msg) ) ; + sprintf( flash_diag_msg, "Adr= %08x, (Adr)= %08x",(UINT32)pw+FLASH_QUERYRCHAR_OFS, + REG32(((UINT32)pw+FLASH_QUERYRCHAR_OFS)) ) ; + rcode = ERROR_FLASH_QRY_NOT_FOUND ; + + } + + /* Verify 'Y' char of the Query-unique ASCII string, part of CFI spec. */ + if ( REG32(pw + 0x12) != FLASH_QUERYYCHAR ) + { + memset( flash_diag_msg, 0, sizeof(flash_diag_msg) ) ; + sprintf( flash_diag_msg, "Adr= %08x, (Adr)= %08x",(UINT32)pw+FLASH_QUERYYCHAR_OFS, + REG32(((UINT32)pw+FLASH_QUERYYCHAR_OFS)) ) ; + rcode = ERROR_FLASH_QRY_NOT_FOUND ; + + } + + /* Issue Reset Command to return to read mode */ + + REG32(pw) = 0x00f000f0; + + return( rcode ) ; + } + + + /************************************************************************ + * + * FLASH_AMD_wait_ready + * Description : + * ------------- + * + * Await FLASH operation completes. + * + * + * Parameters : + * ------------ + * + * - + * + * Return values : + * --------------- + * + * 'OK' = 0x00: File FLASH erased succesfully + * ERROR_FLASH_PROGRAM_ERROR Flash device failure + * + * + ************************************************************************/ + static + INT32 FLASH_AMD_wait_ready(void *pw, long data ) + { + volatile short *pf = (volatile short *)pw; + int a, b; + + a = pf[0]; // initial status + for(;;) + { + b = pf[0]; // read status + if( ((a ^ b) & 0x0040) != 0 ) // if DQ6 toggles + { + if( (b & 0x0020) != 0 ) // if DQ5 set + { + a = pf[0]; + b = pf[0]; + if( ((a ^ b) & 0x0040) == 0 ) // if no toggle + return 0; // show success + else + { + printf("\n"); + return ERROR_FLASH_PROGRAM_ERROR; // else error + } + } + } + else + return OK; // show success if toggle stops + a = b; // prepare for next toggle check + } + } + + + /************************************************************************ + * + * FLASH_AMD_error_lookup + * Description : + * ------------- + * Lookup error code to error string(s) + * + * + * Parameters : + * ------------ + * + * 'p_param', INOUT, variable of type, t_sys_error_string. + * + * + * Return values : + * --------------- + * + * 'OK' = 0x00: + * + * + ************************************************************************/ + static + INT32 FLASH_AMD_error_lookup( t_sys_error_string *p_param ) + { + UINT32 t, i ; + + i = 0 ; + p_param->count = 0 ; + t = SYSERROR_ID( p_param->syserror ) ; + if ( flash_last_error == p_param->syserror ) + { + /* check for recognized error code */ + if (t < sizeof(flash_error_string)/sizeof(char*) ) + { + /* fill in mandatory error message string */ + p_param->strings[SYSCON_ERRORMSG_IDX] = flash_error_string[t] ; + i++ ; + + /* check for diagnose message */ + if ( flash_diag_msg[0] != 0 ) + { + /* fill in optional diagnose message string */ + p_param->strings[SYSCON_DIAGMSG_IDX] = flash_diag_msg ; + i++ ; + } + + /* check for hint message */ + if ( flash_error_hint_string[t] != NULL) + { + /* fill in optional hint message string */ + p_param->strings[SYSCON_HINTMSG_IDX] = flash_error_hint_string[t] ; + i++ ; + } + } + p_param->count = i ; + } + + /* delete context */ + flash_last_error = OK ; + return(OK) ; + } + + /************************************************************************ + * + * FLASH_AMD_is_system_flash_write_protected + * Description : + * ------------- + * Check if system flash id write protected + * + * + * Parameters : + * ------------ + * + * + * + * Return values : + * --------------- + * + * FALSE: not write protected + * TRUE: write protected + * + * + ************************************************************************/ + static + bool FLASH_AMD_is_system_flash_write_protected( void ) + { + UINT32 rcode ; + UINT32 wr_protect ; + + return FALSE; // *** Kludge *** + + /* check in SYSCON */ + rcode = SYSCON_read( SYSCON_BOARD_SYSTEMFLASH_WRITE_PROTECTED_ID, + &wr_protect, + sizeof(wr_protect) ) ; + if (wr_protect) + { + return( TRUE ) ; + } + else + { + return( FALSE ) ; + } + } + + + /************************************************************************ + * + * FLASH_AMD_is_file_flash_write_protected + * Description : + * ------------- + * Check if file flash id write protected + * + * + * Parameters : + * ------------ + * + * + * + * Return values : + * --------------- + * + * FALSE: not write protected + * TRUE: write protected + * + * + ************************************************************************/ + static + bool FLASH_AMD_is_file_flash_write_protected( void ) + { + UINT32 rcode ; + UINT32 wr_protect ; + + return FALSE; // *** Kludge *** + + /* check in SYSCON */ + rcode = SYSCON_read( SYSCON_BOARD_FILEFLASH_WRITE_PROTECTED_ID, + &wr_protect, + sizeof(wr_protect) ) ; + if (wr_protect) + { + return( TRUE ) ; + } + else + { + return( FALSE ) ; + } + } + + + /************************************************************************ + * + * FLASH_AMD_is_monitor_flash_write_protected + * Description : + * ------------- + * Check if file flash id write protected + * + * + * Parameters : + * ------------ + * + * + * + * Return values : + * --------------- + * + * FALSE: not write protected + * TRUE: write protected + * + * + ************************************************************************/ + static + bool FLASH_AMD_is_monitor_flash_write_protected( void ) + { + UINT32 rcode ; + UINT32 wr_protect ; + + return FALSE; // *** Kludge *** + + /* check in SYSCON */ + rcode = SYSCON_read( SYSCON_BOARD_MONITORFLASH_WRITE_PROTECTED_ID, + &wr_protect, + sizeof(wr_protect) ) ; + if (wr_protect) + { + return( TRUE ) ; + } + else + { + return( FALSE ) ; + } + } diff -cNr yamon-sde6/drivers/lan/lan_au1x00.c yamon-devdrv/drivers/lan/lan_au1x00.c *** yamon-sde6/drivers/lan/lan_au1x00.c Thu Jan 1 09:00:00 1970 --- yamon-devdrv/drivers/lan/lan_au1x00.c Tue Sep 27 16:34:26 2005 *************** *** 0 **** --- 1,1739 ---- + + /************************************************************************ + * + * LAN_AU1X00.c + * + * The 'LAN_AU1X00' module implements the LAN_AU1X00 + * device driver as an IO device with following services: + * + * 1) init serial device: configure and initialize MAC + * AU1X00 driver + * 2) open serial device: register receive handler + * 3) close serial device: not used + * 4) read serial device: poll for received frame + * 5) write serial device: request frame to be transmitted + * 6) ctrl serial device: not used + * + * + * ###################################################################### + * + * This program is largely copies by the MAC_AU1X00(made by AMD) + * source files. + * + * Copyright 2005 Device Drivers Limited. + * Author: kawamoto@devdrv.co.jp + * + ************************************************************************/ + + + + + /************************************************************************ + * Include files + ************************************************************************/ + + #include + #include + #include + #include + #include + #include + #include + #include + #include + #include + + + /* #define ETH_DEBUG 1 */ + /************************************************************************ + * Constant Definitions + *************************************************************************/ + + typedef enum + { + MAC0_MINOR_AU1X00_DEVICE = 0, /* There are two MACs on the AU1X00 */ + MAC1_MINOR_AU1X00_DEVICE = 1, + MAC_MINOR_AU1X00_DEVICES + }t_MAC_MINOR_AU1X00_devices ; + + + /* PHY definitions */ + + #define PHY_ADDRESS 0 + #define PHY_CONTROL_DEFAULT 0x3000 + + + /* TX and RX packet size: fixed to 2048 bytes This will accomodate the worst case + receive size */ + + #define MAC_AU1X00_PACKET_SIZE 2048 + + /* Number of TX buffers = number of RX buffers = 4 */ + + #define MAC_AU1X00_TX_BUFFERS 4 + #define MAC_AU1X00_RX_BUFFERS 4 + + /* To enable the AU1X00 MAC tossing */ + + #define DISABLE_TOSS 0 + #define ENABLE_TOSS 1 + + /* Minimum packet size - 64 is spec but 4 bytes will be taken automatically by FCS */ + #define MAC_AU1X00_MIN_PACKET_SIZE 60 + + + /************************************************************************ + * Macro Definitions + *************************************************************************/ + + + #define IF_ERROR( completion, function ) \ + { \ + completion = function ; \ + if ( completion != OK ) \ + { \ + return( completion ) ; \ + } \ + } + + /* This is a redefinition of reg without appending OFS to the offs definition */ + + #define MACREG(base,offs) (*((volatile UINT32 *)((UINT32)(base) + offs) )) + + #define SET(f) (1< Resets MAC, 1-> Enables MAC */ + #define MAC_ENABLE_MACCLK 0 /* New Mac Enable Bit Location */ + + /* Global driver states - the numbers are arbitrary */ + #define MAC_AU1X00_DRIVER_IS_STOPPED 0x42 + #define MAC_AU1X00_DRIVER_IS_STARTED 0x44 + + /************************************************************************ + * MAC AU1X00: DMA Address/Enable Register Bits + *************************************************************************/ + + #define MAC_DMA_ADDR 5 /* 27 bits: Address field starting at bit 5 */ + #define MAC_DMA_NEXTBUF 2 /* 2 bits: next buffer to be used by DMA*/ + #define MAC_DMA_DONE 1 /* MAC DMA Done bit */ + #define MAC_DMA_ENABLE 0 /* MAC DMA Enable bit */ + + #define MAC_DMA_ADDR_MASK 0xFFFFFFE0 + #define MAC_DMA_NEXTBUF_MASK (0x3 << MAC_DMA_NEXTBUF) + + #define MAC_DMA_DONE_MASK 0x02 + #define MAC_DMA_ENABLE_MASK 0x01 + #define MAC_DMA_DISABLE_MASK ~MAC_DMA_ENABLE_MASK + + #define MAC_DMA_READY_MASK 0x3 + + + /*********************************************************************\ + * MAC Transmit Status Bit Fields * + \*********************************************************************/ + #define MAC_TRANSMIT_PR 31 /* Packet Retry */ + /* 30-14 Reserved */ + #define MAC_TRANSMIT_CC 10 /* 4-bit Collision Count */ + #define MAC_TRANSMIT_LO 9 /* Late Collision Observed (retried) */ + #define MAC_TRANSMIT_DF 8 /* Deferred */ + #define MAC_TRANSMIT_UR 7 /* Data Under Run */ + #define MAC_TRANSMIT_EC 6 /* Excessive Collisions */ + #define MAC_TRANSMIT_LC 5 /* Late Collision */ + #define MAC_TRANSMIT_ED 4 /* Excessive Defferal */ + #define MAC_TRANSMIT_LS 3 /* Loss of Carrier */ + #define MAC_TRANSMIT_NC 2 /* No Carrier */ + #define MAC_TRANSMIT_JT 1 /* Jabber Timeout */ + #define MAC_TRANSMIT_FA 0 /* Frame Abort */ + + #define MAC_TRANSMIT_CC_MASK (0xf << MAC_TRANSMIT_CC) + #define MAC_TRANSMIT_UR_MASK (1 << MAC_TRANSMIT_UR) + #define MAC_TRANSMIT_EC_MASK (1 << MAC_TRANSMIT_EC) + #define MAC_TRANSMIT_LC_MASK (1 << MAC_TRANSMIT_LC) + #define MAC_TRANSMIT_ED_MASK (1 << MAC_TRANSMIT_ED) + #define MAC_TRANSMIT_LS_MASK (1 << MAC_TRANSMIT_LS) + #define MAC_TRANSMIT_NC_MASK (1 << MAC_TRANSMIT_NC) + #define MAC_TRANSMIT_JT_MASK (1 << MAC_TRANSMIT_JT) + #define MAC_TRANSMIT_FA_MASK (1 << MAC_TRANSMIT_FA) + + /*********************************************************************\ + * MAC Receive Status Bit Fields * + \*********************************************************************/ + #define MAC_RECEIVE_MI 31 /* Missed Frame */ + #define MAC_RECEIVE_PF 30 /* Packet Filter */ + #define MAC_RECEIVE_FF 29 /* Filtering Fail */ + #define MAC_RECEIVE_BF 28 /* Broadcast Frame */ + #define MAC_RECEIVE_MF 27 /* MultiCast Frame */ + #define MAC_RECEIVE_UC 26 /* Unsupprted Control Frame */ + #define MAC_RECEIVE_CF 25 /* Control Frame */ + #define MAC_RECEIVE_LE 24 /* Length Error */ + #define MAC_RECEIVE_V2 23 /* VLAN 2 Frame Check */ + #define MAC_RECEIVE_V1 22 /* VLAN 1 Frame Check */ + #define MAC_RECEIVE_CR 21 /* CRC Error */ + #define MAC_RECEIVE_DB 20 /* Dribble Bit */ + #define MAC_RECEIVE_ME 19 /* MII Error (MII_Rxer) */ + #define MAC_RECEIVE_FT 18 /* Frame Type (1-Ethernet 0-802.3) */ + #define MAC_RECEIVE_CS 17 /* Collision Seen */ + #define MAC_RECEIVE_FL 16 /* Frame Too Long */ + #define MAC_RECEIVE_RF 15 /* Runt Frame */ + #define MAC_RECEIVE_WT 14 /* Watch Dog Timeout */ + #define MAC_RECEIVE_L 0 /* 14 bit Frame Length */ + + #define MAC_RECEIVE_MI_MASK (1 << MAC_RECEIVE_MI) + #define MAC_RECEIVE_PF_MASK (1 << MAC_RECEIVE_PF) + #define MAC_RECEIVE_FF_MASK (1 << MAC_RECEIVE_FF) + #define MAC_RECEIVE_BF_MASK (1 << MAC_RECEIVE_BF) + #define MAC_RECEIVE_MF_MASK (1 << MAC_RECEIVE_MF) + #define MAC_RECEIVE_UC_MASK (1 << MAC_RECEIVE_UC) + #define MAC_RECEIVE_CF_MASK (1 << MAC_RECEIVE_CF) + #define MAC_RECEIVE_LE_MASK (1 << MAC_RECEIVE_LE) + #define MAC_RECEIVE_V2_MASK (1 << MAC_RECEIVE_V2) + #define MAC_RECEIVE_V1_MASK (1 << MAC_RECEIVE_V1) + #define MAC_RECEIVE_CR_MASK (1 << MAC_RECEIVE_CR) + #define MAC_RECEIVE_DB_MASK (1 << MAC_RECEIVE_DB) + #define MAC_RECEIVE_ME_MASK (1 << MAC_RECEIVE_ME) + #define MAC_RECEIVE_FT_MASK (1 << MAC_RECEIVE_FT) + #define MAC_RECEIVE_CS_MASK (1 << MAC_RECEIVE_CS) + #define MAC_RECEIVE_FL_MASK (1 << MAC_RECEIVE_FL) + #define MAC_RECEIVE_RF_MASK (1 << MAC_RECEIVE_RF) + #define MAC_RECEIVE_WT_MASK (1 << MAC_RECEIVE_WT) + #define MAC_RECEIVE_L_MASK (0x3fff << MAC_RECEIVE_L) + + /************************************************************************ + * Public variables + ************************************************************************/ + + /************************************************************************ + * Static variables + ************************************************************************/ + static UINT32 poll_count = 0 ; + static char msg[160] ; + + /* Global driver state */ + static UINT32 MAC_AU1X00_state = MAC_AU1X00_DRIVER_IS_STOPPED ; + + /* MAC broadcast address */ + static t_mac_addr mac_broadcast_adr = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff } ; + + /* User registered receive handler */ + static UINT32 (*usr_receive)( UINT32 length, UINT8 *data ) = NULL ; + + /* Device context per minor device for this driver */ + static t_MAC_AU1X00_device minor_device[MAC_MINOR_AU1X00_DEVICES] ; + + /* Dynamic allocated memory */ + static void *lan_dma_buffers = NULL ; + + /************************************************************************ + * Static function prototypes, local helper functions + ************************************************************************/ + + static INT32 MAC_AU1X00_allocate_buffers( t_MAC_AU1X00_device *pdevice ) ; + static INT32 MAC_AU1X00_stop( t_MAC_AU1X00_device *pdevice ) ; + static INT32 MAC_AU1X00_MII_init( t_MAC_AU1X00_device *pdevice ) ; + static INT32 MAC_AU1X00_MII_status( t_MAC_AU1X00_device *pdevice ) ; + static INT32 MAC_AU1X00_control_init( t_MAC_AU1X00_device *pdevice ) ; + static INT32 MAC_AU1X00_DMA_init( t_MAC_AU1X00_device *pdevice ) ; + static INT32 MAC_AU1X00_dump_regs( t_MAC_AU1X00_device *pdevice ) ; + static INT32 MAC_AU1X00_dump_status( t_MAC_AU1X00_device *pdevice ) ; + void bosporus_init_switch(); + + /************************************************************************ + * Static function prototypes, device driver IO functions + ************************************************************************/ + + static + INT32 LAN_AU1X00_init( + UINT32 major, /* IN: major device number */ + UINT32 minor, /* IN: minor device number */ + void *p_param ) ; /* INOUT: device parameter block */ + + static + INT32 LAN_AU1X00_open( + UINT32 major, /* IN: major device number */ + UINT32 minor, /* IN: minor device number */ + t_LAN_OPEN_desc *p_param ) ; /* IN: receive handler reference */ + + static + INT32 LAN_AU1X00_read( + UINT32 major, /* IN: major device number */ + UINT32 minor, /* IN: minor device number */ + t_LAN_IO_desc *p_param ) ; /* INOUT: LAN frame */ + + static + INT32 LAN_AU1X00_write( + UINT32 major, /* IN: major device number */ + UINT32 minor, /* IN: minor device number */ + t_LAN_IO_desc *p_param ) ; /* OUT: frame to transmit */ + + static + INT32 LAN_AU1X00_ctrl( + UINT32 major, /* IN: major device number */ + UINT32 minor, /* IN: minor device number */ + t_LAN_CTRL_desc *p_param ) ; /* IN-OUT: */ + + + /************************************************************************ + * Implementation : Public functions + ************************************************************************/ + + + /************************************************************************ + * + * LAN_AU1X00_install + * Description : + * ------------- + * + * Installs the AU1X00 LAN device drivers services in + * the IO system at the reserved device slot, found in the + * 'sysdev.h' file, which defines all major device numbers. + * + * Note: + * This service is the only public declared interface function; all + * provided device driver services are static declared, but this + * function installs the function pointers in the io-system to + * enable the provided public driver services. + * + * Parameters : + * ------------ + * + * - + * + * + * Return values : + * --------------- + * + * 'OK'(=0) + * 'ERROR_IO_ILLEGAL_MAJOR': Illegal major device number + * 'ERROR_IO_NO_SPACE': Device slot already allocated + * + ************************************************************************/ + INT32 LAN_AU1X00_install( void ) + { + /* pre-initialize local variables and install device services */ + memset(minor_device, sizeof(minor_device), 0); + IO_install(SYS_MAJOR_LAN_AU1X00, /* major device number */ + (t_io_service)LAN_AU1X00_init, /* 'init' service */ + (t_io_service)LAN_AU1X00_open, /* 'open' service */ + NULL, /* 'close' service na */ + (t_io_service)LAN_AU1X00_read, /* 'read' service */ + (t_io_service)LAN_AU1X00_write, /* 'write' service */ + (t_io_service)LAN_AU1X00_ctrl); /* 'ctrl' service */ + + /* initialize MAC AU1X00 device driver */ + if(IO_init( SYS_MAJOR_LAN_AU1X00, 0, NULL ) != OK) + { + /* Should not happen unless board is defect */ + IO_deinstall(SYS_MAJOR_LAN_AU1X00); + } + return OK; + } + + + /************************************************************************ + * Implementation : Static functions + ************************************************************************/ + + + /************************************************************************ + * Implementation : Local helper functions + ************************************************************************/ + + + /************************************************************************ + * + * MAC_AU1X00_allocate_buffers + * Description : + * ------------- + * This routine allocates memory for: + * + * - Receive buffers + * - Transmit buffer + * + * + * Parameters : + * ------------ + * + * 'pdevice', IN, reference for this device context + * + * + * Return values : + * --------------- + * + * 'OK'(=0) + * + * + * + ************************************************************************/ + static + INT32 MAC_AU1X00_allocate_buffers( t_MAC_AU1X00_device *pdevice ) + { + INT32 rcode ; + t_sys_malloc mem ; + void *Pa; + UINT32 i, j ; + + if(lan_dma_buffers == NULL) + { + /* allocate all RX and TX packets in one chunk on a 2K boundary. */ + mem.size= MAC_AU1X00_PACKET_SIZE * MAC_AU1X00_TX_BUFFERS + + MAC_AU1X00_PACKET_SIZE * MAC_AU1X00_RX_BUFFERS; + mem.boundary = MAC_AU1X00_PACKET_SIZE; + mem.memory = &Pa; + + /* request RX and TX memory in one chunk */ + rcode = SYSCON_read( SYSCON_BOARD_MALLOC_ID, + &mem, + sizeof(t_sys_malloc) ) ; + if (rcode != OK) + { + return( rcode ) ; + } + + /* cache this reference */ + lan_dma_buffers = Pa ; + } + else + { + /* not first time */ + Pa = lan_dma_buffers; + } + + /* Initialize buffer space */ + mem.size = MAC_AU1X00_PACKET_SIZE * MAC_AU1X00_TX_BUFFERS + + MAC_AU1X00_PACKET_SIZE * MAC_AU1X00_RX_BUFFERS; + + Pa = (void*) KSEG1((UINT32)Pa); + memset( Pa, 0, mem.size ); + + /* Init RX buffer pointers */ + for ( i=0; i < MAC_AU1X00_RX_BUFFERS; i++ ) + { + pdevice->RcvBuffer[i] = PHYS((UINT32) Pa); + Pa += MAC_AU1X00_PACKET_SIZE ; + } + + /* Init TX buffer pointers */ + for ( i=0; i < MAC_AU1X00_TX_BUFFERS; i++ ) + { + pdevice->TxmBuffer[i] = PHYS((UINT32) Pa); + Pa += MAC_AU1X00_PACKET_SIZE ; + } + + return( OK ); + } + + + /************************************************************************ + * + * MAC_AU1X00_stop + * Description : + * ------------- + * This routine stops the AU1X00 LAN controller + * by stoping DMA transfer and resetting the chip. + * + * + * Parameters : + * ------------ + * + * 'pdevice', IN, reference for this device context + * + * + * Return values : + * --------------- + * + * 'OK'(=0) + * + * + * + ************************************************************************/ + static + INT32 MAC_AU1X00_stop( t_MAC_AU1X00_device *pdevice ) + { + int i; + + /* Clear active low Reset Bits and set DMA RESET (active high) */ + MACREG( pdevice->pAU1X00EnReg, MAC_ENABLE ) = SET(MAC_ENABLE_DMARESET); + + /* Clear Enable for Tx DMA */ + + for (i=0; i< MAC_AU1X00_TX_BUFFERS ; i++) { + + MACREG( pdevice->pAU1X00DMARegs, + SETV(DMA_TRANSMIT, MAC_DMA_TXRX) | + SETV(i,MAC_DMA_BUF) | /* i selects buffer to disable */ + SETV(DMA_ADDRESS_EN ,MAC_DMA_REG) ) + = 0 /*&= MAC_DMA_DISABLE_MASK*/; + } + + /* Clear Enable for Rx DMA */ + + for (i=0; i< MAC_AU1X00_RX_BUFFERS ; i++) { + + MACREG( pdevice->pAU1X00DMARegs, + SETV(DMA_RECEIVE , MAC_DMA_TXRX) | + SETV(i,MAC_DMA_BUF) | /* i selects buffer to disable */ + SETV(DMA_ADDRESS_EN ,MAC_DMA_REG) ) + = 0 /*&= MAC_DMA_DISABLE_MASK*/; + } + + MAC_AU1X00_state = MAC_AU1X00_DRIVER_IS_STOPPED; + + return( OK ); + } + + + + /************************************************************************ + * + * MAC_AU1X00_MII_init + * Description : + * ------------- + * Initialize physical device + * + * + * Parameters : + * ------------ + * + * 'pdevice', IN, reference for this device context + * + * + * Return values : + * --------------- + * + + * 'OK'(=0) + * + * + * + ************************************************************************/ + static MAC_MII_WRITE( + t_MAC_AU1X00_device *pdevice, + int reg, int val + ) + { + /* check link status, spin here till done */ + while ( MACREG( pdevice->pAU1X00CtrlRegs, MAC_MIICTRL) + & MAC_MIICTRL_MBUSY_MASK) ; + + MACREG(pdevice->pAU1X00CtrlRegs, MAC_MIIDATA) = val; + MACREG(pdevice->pAU1X00CtrlRegs, MAC_MIICTRL) = (reg << 6) | 0x02; + + /* check link status, spin here till done */ + while ( MACREG( pdevice->pAU1X00CtrlRegs, MAC_MIICTRL) + & MAC_MIICTRL_MBUSY_MASK) ; + } + + static int MAC_MII_READ( + t_MAC_AU1X00_device *pdevice, + int reg + ) + { + /* check link status, spin here till done */ + while ( MACREG( pdevice->pAU1X00CtrlRegs, MAC_MIICTRL) + & MAC_MIICTRL_MBUSY_MASK) ; + + MACREG(pdevice->pAU1X00CtrlRegs, MAC_MIICTRL) = (reg << 6); + + /* check link status, spin here till done */ + while ( MACREG( pdevice->pAU1X00CtrlRegs, MAC_MIICTRL) + & MAC_MIICTRL_MBUSY_MASK) ; + + return MACREG(pdevice->pAU1X00CtrlRegs, MAC_MIIDATA); + } + + static + INT32 MAC_AU1X00_MII_init( t_MAC_AU1X00_device *pdevice ) + { + int i ; + INT32 rcode ; + + #ifdef PB1000_CONFIG + DISP_STR("No MII Init"); + #endif + + #ifdef HYDROGEN_CONFIG + DISP_STR("No MII Init"); + #endif + + #ifdef HYD1100_CONFIG + DISP_STR("No MII Init"); + #endif + + #ifdef BE1000_CONFIG + DISP_STR("MII INIT"); + MAC_MII_WRITE(pdevice,0,0x3200); // reset Autonegotiation + MAC_MII_WRITE(pdevice,17,0xffc0); // set LEDs to display correctly + #endif + + #ifdef BOSPORUS_CONFIG + DISP_STR("SWITCH INIT"); + bosporus_init_switch(); + #endif + + #ifdef PB1500_CONFIG + DISP_STR("MII INIT"); + MAC_MII_WRITE(pdevice,0,0x3200); // reset Autonegotiation + MAC_MII_WRITE(pdevice,17,0xffc0); // set LEDs to display correctly + #endif + + #ifdef PB1100_CONFIG + DISP_STR("MII INIT"); + MAC_MII_WRITE(pdevice,0,0x3200); // reset Autonegotiation + MAC_MII_WRITE(pdevice,17,0xffc0); // set LEDs to display correctly + #endif + + #ifdef DB1500_CONFIG + DISP_STR("AMD PHY INIT GOES HERE"); + #endif + + return(OK); + + #ifdef TI1500_CONFIG + DISP_STR("TI1500 AMD PHY INIT GOES HERE"); + #endif + + return(OK) ; + } + + + /************************************************************************ + * + * MAC_AU1X00_control_init + * Description : + * ------------- + * This routine initialize the AU1X00 Control Register + * + * + * Parameters : + * ------------ + * + * 'pdevice', IN, reference for this device context + * + * + * Return values : + * --------------- + * + * 'OK'(=0) + * + * + * + ************************************************************************/ + static + INT32 MAC_AU1X00_control_init( t_MAC_AU1X00_device *pdevice ) + { + + INT32 rcode; + int i; + + t_mac_addr mac_addr ; + + /* get MAC address from board */ + IF_ERROR( (rcode), + (SYSCON_read( SYSCON_COM_EN0_MAC_ADDR_ID, + &(mac_addr), + sizeof(mac_addr)) ) ) + + for(i=0;i<6;i++) + pdevice->PhysicalAddress[i] = mac_addr[i]; + + /* Bring MAC out of Reset */ + + /* Enable CLocks */ + + MACREG( pdevice->pAU1X00EnReg, MAC_ENABLE) = SET(MAC_ENABLE_MACCLK) | + SET(MAC_ENABLE_DMARESET); + + /* Bring out of reset */ + + MACREG( pdevice->pAU1X00EnReg, MAC_ENABLE) = SET(MAC_ENABLE_TXEN) | + SET(MAC_ENABLE_MIIENAB) | + SET(MAC_ENABLE_MACINIT) | + SET(MAC_ENABLE_MACCLK); + + /* Turn off promiscuous mode - other than that defaults should be OK */ + + + MACREG( pdevice->pAU1X00CtrlRegs, MAC_CONTROL) = SETV(0, MAC_CONTROL_PR) | + #ifdef EB + SET(MAC_CONTROL_EM) | /* Big Endian */ + #endif + SET(MAC_CONTROL_DO) | /* Disable Receive Own */ + SET(MAC_CONTROL_DB); /* Disable Broadcast Frames */ + + /* Program Address - The LSB of low address is the first bit to compare on receive + so this needs to contain the first byte to be compared */ + + MACREG( pdevice->pAU1X00CtrlRegs, MAC_ADDRLO) = pdevice->PhysicalAddress[0] | + pdevice->PhysicalAddress[1] << 8 | + pdevice->PhysicalAddress[2] << 16| + pdevice->PhysicalAddress[3] << 24; + + MACREG( pdevice->pAU1X00CtrlRegs, MAC_ADDRHI) = pdevice->PhysicalAddress[4] | + pdevice->PhysicalAddress[5] << 8; + return( OK ); + } + + + /************************************************************************ + * + * MAC_AU1X00_DMA_init + * Description : + * ------------- + * Setup the AU1X00 DMA registers + * + * + * Parameters : + * ------------ + * + * 'pdevice', IN, reference for this device context + * + * + * Return values : + * --------------- + * + * 'OK'(=0) + * + * + * + ************************************************************************/ + static + INT32 MAC_AU1X00_DMA_init( t_MAC_AU1X00_device *pdevice ) + { + int i; + + /* The DMA registers will not be clobbered in reset. The MAC registers will be */ + /* This means the DMA can be setup before the MAC is brought out of reset but the + MAC can not be */ + + /* Get next buffer location for DMA before setting EN=1 */ + + pdevice->NextRcvBufferIndex = (MACREG( pdevice->pAU1X00DMARegs, + SETV(DMA_RECEIVE, MAC_DMA_TXRX) | + SETV(DMA_ADDRESS_EN,MAC_DMA_REG)) & + MAC_DMA_NEXTBUF_MASK) >> MAC_DMA_NEXTBUF; + + /* Setup DMA Address for Rx */ + + for (i=0; i< MAC_AU1X00_RX_BUFFERS ; i++) { + + MACREG( pdevice->pAU1X00DMARegs, + SETV(DMA_RECEIVE, MAC_DMA_TXRX) | + SETV(i,MAC_DMA_BUF) | /* i selects buffer */ + SETV(DMA_ADDRESS_EN ,MAC_DMA_REG) ) + |= pdevice->RcvBuffer[i] & MAC_DMA_ADDR_MASK; /* only upper 27 bits are used */ + } + + return( OK ); + } + + + + + /************************************************************************ + * Implementation : Device driver services + ************************************************************************/ + + + + /************************************************************************ + * + * LAN_AU1X00_init + * Description : + * ------------- + * This service initializes the lan driver and configures + * the MAC-address for the 'EN0' LAN interface. + * The MAC-address is read during 'init' via the 'syscon' parameter: + * -'SYSCON_COM_EN0_MAC_ADDR_ID'. + * + * + * Parameters : + * ------------ + * + * 'major', IN, major device number + * 'minor', IN, not used + * 'p_param', INOUT, not used + * + * + * Return values : + * --------------- + * + * 'OK'(=0) + * + * + * + ************************************************************************/ + static + INT32 LAN_AU1X00_init( + UINT32 major, /* IN: major device number */ + UINT32 minor, /* IN: minor device number */ + void *p_param ) /* INOUT: device parameter block */ + { + INT32 rcode; + int i; + UINT32 prid; + + minor_device[minor].pAU1X00CtrlRegs = (UINT32*) MAC0_AU1X00_BASE; + minor_device[minor].pAU1X00EnReg = (UINT32*) MAC0_AU1X00_EN_BASE; + minor_device[minor].pAU1X00DMARegs = (UINT32*) MAC0_AU1X00_DMA_BASE; + + #ifdef ETH_DEBUG + sprintf( msg, "\n\r MAC_AU1X00_init: %08x\n\r", (UINT32) minor_device[minor].pAU1X00CtrlRegs ) ; + PUTS( DEFAULT_PORT, msg ) ; + #endif + + + /* allocate MAC RX/TX frame buffer space */ + IF_ERROR( (rcode), + (MAC_AU1X00_allocate_buffers(&minor_device[minor])) ) + + /* Stop any active DMA */ + IF_ERROR( (rcode), + (MAC_AU1X00_stop(&minor_device[minor])) ) + + /* Reset MAC out of reset and program address */ + IF_ERROR( (rcode), + (MAC_AU1X00_control_init(&minor_device[minor])) ) + + + /* initialize AU1X00 DMA context registers */ + IF_ERROR( (rcode), + (MAC_AU1X00_DMA_init(&minor_device[minor])) ) + + /* initialize AU1X00 MII */ + IF_ERROR( (rcode), + (MAC_AU1X00_MII_init(&minor_device[minor])) ) + + /* Enable All 4 Receive DMA Here */ + + /* Revise: Since all processing is polled, we are assuming that receives will be solicited and + will not occur at unknown times, this is an assumption */ + + for (i=0; i< MAC_AU1X00_RX_BUFFERS ; i++) { + + MACREG( minor_device[minor].pAU1X00DMARegs, + SETV(DMA_RECEIVE, MAC_DMA_TXRX) | + SETV(i,MAC_DMA_BUF) | /* i selects buffer to enable */ + SETV(DMA_ADDRESS_EN ,MAC_DMA_REG) ) + |= MAC_DMA_ENABLE_MASK; + } + + + /* Enable TX and RX */ + MACREG( minor_device[minor].pAU1X00CtrlRegs, MAC_CONTROL ) |= SET(MAC_CONTROL_TE) | SET(MAC_CONTROL_RE); + + + #ifdef ETH_DEBUG + /* dump AU1X00 LAN controller registers */ + IF_ERROR( (rcode), + (MAC_AU1X00_dump_regs(&minor_device[minor])) ) + #endif + + MAC_AU1X00_state = MAC_AU1X00_DRIVER_IS_STARTED; + + return( OK ) ; + } + + + /************************************************************************ + * + * MAC_AU1X00_open + * Description : + * ------------- + * This service registers a mac-layer defined receive-handler in the + * LAN-drivers ISR-context to allow for interrupt controlled receive + * frame processing in the network stack. No external buffer + * administration is required as the protocol-layers are responsible for + * handling buffer-allocation and data copy-ing to the allocated buffer + * payload area. At return from 'receive' handler, the LAN-drivers + * local RX-buffer (packet) is released for re-use. After 'open' + * has been called, the LAN-driver's 'read' service will call the + * registered receive-handler by any frame reception with direct + * reference to the LAN-drivers packet space and no read data will be + * delivered in the IO-descriptor. + * + * + * + * Parameters : + * ------------ + * + * 'major', IN, major device number + * 'minor', IN, not used + * 'p_param', IN, LAN variable of type, t_LAN_IO_desc. + * + * + * Return values : + * --------------- + * 'OK'(=0) + * + * + * + ************************************************************************/ + static + INT32 LAN_AU1X00_open( + UINT32 major, /* IN: major device number */ + UINT32 minor, /* IN: minor device number */ + t_LAN_OPEN_desc *p_param ) /* IN: receive handler reference */ + { + /* register user defined receive handler */ + usr_receive = p_param->receive ; + + return( OK ) ; + } + + + + /************************************************************************ + * + * MAC_AU1X00_read + * Description : + * ------------- + * This service polls the specified LAN interface for any received frame. + * If any frame has been received, it will be read into the user allocated + * variable, *p_param; if none present, completion = 'ERROR_LAN_NO_FRAME' + * will be returned. + * + * + * Parameters : + * ------------ + * + * 'major', IN, major device number + * 'minor', IN, minor device number for multi device drivers + * 'p_param', INOUT, LAN variable of type, t_LAN_IO_desc. + * + * + * Return values : + * --------------- + * + * 'OK'(=0) + * 'ERROR_LAN_NO_FRAME': no frame present on this LAN interface + * 'ERROR_LAN_COMM_ERROR': communication error detected + * + * + ************************************************************************/ + static + INT32 LAN_AU1X00_read( + UINT32 major, /* IN: major device number */ + UINT32 minor, /* IN: minor device number */ + t_LAN_IO_desc *p_param ) /* INOUT: LAN frame */ + { + int BufferIndex; + int PacketIndex; + UINT32 status ; + UINT32 *pPacket; + UINT32 wBufLen ; + UINT8 *address; + t_MAC_AU1X00_device *pdevice ; + static int first = 1; + + UINT32 rc = ERROR_LAN_NO_FRAME ; + UINT8 *pbData = p_param->data ; + UINT32 dwLength = p_param->length ; + + + if ( MAC_AU1X00_state == MAC_AU1X00_DRIVER_IS_STOPPED ) + { + return( ERROR_LAN_NO_FRAME ) ; + } + + + /* get device context for this minor device */ + pdevice = &minor_device[minor] ; + + + while (1) + { + /* address next packet */ + + BufferIndex = pdevice->NextRcvBufferIndex; + + + if ( MACREG( pdevice->pAU1X00DMARegs, + SETV(DMA_RECEIVE, MAC_DMA_TXRX) | + SETV(BufferIndex,MAC_DMA_BUF) | /* BufferIndex picks correct DMA register */ + SETV(DMA_ADDRESS_EN ,MAC_DMA_REG)) + & MAC_DMA_DONE_MASK ) /* If DONE then a receive has taken place */ + { + + status = MACREG( pdevice->pAU1X00DMARegs, + SETV(DMA_RECEIVE, MAC_DMA_TXRX) | + SETV(BufferIndex,MAC_DMA_BUF) | /* BufferIndex picks correct DMA register */ + SETV(DMA_STATUS ,MAC_DMA_REG)); + + /* check for missed frame */ + if ( status & MAC_RECEIVE_MI_MASK ) + { + /* received packet has errors, drop this packet */ + pdevice->status.rx_errors++; + if (status & MAC_RECEIVE_CR_MASK) + pdevice->status.rx_cr_errors++; + + if (status & MAC_RECEIVE_DB_MASK) + pdevice->status.rx_db_errors++; + + if (status & MAC_RECEIVE_FL_MASK) + pdevice->status.rx_fl_errors++; + + if (status & MAC_RECEIVE_MI_MASK) + pdevice->status.rx_mi_errors++; + } + else if( !(status & MAC_RECEIVE_PF_MASK)) + { + /* Broadcast Frame ? */ + pdevice->status.rx_pf_errors++; + } + else /* received packet is good */ + { + + pPacket = (UINT32*)KSEG0(pdevice->RcvBuffer[BufferIndex]); + + wBufLen = status & MAC_RECEIVE_L_MASK ; + + pdevice->status.rx_bytes += wBufLen; + + pdevice->status.rx_packets++; + + if (usr_receive != NULL) + { + /* we have a registered receive handler */ + if ( wBufLen == 0 ) + { + /* drop the packet */ + pdevice->status.rx_zero_length_errors++; + } + else + { + /* count any broadcast's */ + if ( !memcmp( ((UINT8*)pPacket), mac_broadcast_adr, SYS_MAC_ADDR_SIZE ) ) + { + pdevice->status.multicast++ ; + } + + /* call the handler */ + (*usr_receive)( wBufLen, ((UINT8*)pPacket)) ; + + /* packet processed */ + rc = OK; + } + } + else + { + /* we don't have a registered receive handler */ + + if ( wBufLen == 0 ) + { + /* drop the packet */ + pdevice->status.rx_zero_length_errors++; + } + + if ( wBufLen > dwLength ) + { + /* drop the packet */ + pdevice->status.rx_buffer_length_errors++; + } + else + { + /* count any broadcast's */ + if ( !memcmp( ((UINT8*)pPacket), mac_broadcast_adr, SYS_MAC_ADDR_SIZE ) ) + { + pdevice->status.multicast++ ; + } + address = (UINT8* ) pPacket; + memcpy ( pbData, (UINT8* )address, wBufLen); + + /* we got the packet, return */ + rc = OK; + } + } + + + } + + /* Enable Current buffer again since we are done */ + + MACREG( pdevice->pAU1X00DMARegs, + SETV(DMA_RECEIVE, MAC_DMA_TXRX) | + SETV(BufferIndex,MAC_DMA_BUF) | /* i selects buffer */ + SETV(DMA_ADDRESS_EN ,MAC_DMA_REG) ) + = (pdevice->RcvBuffer[BufferIndex] & MAC_DMA_ADDR_MASK) | MAC_DMA_ENABLE_MASK; /* only upper 27 bits are used */ + + /* Increment Next Buffer */ + + pdevice->NextRcvBufferIndex++; + + if ( pdevice->NextRcvBufferIndex >= MAC_AU1X00_RX_BUFFERS ) + { + pdevice->NextRcvBufferIndex = 0; + } + /* check for any received packet */ + if (rc == OK) + { + return(OK) ; + } + } + else + { + /* no more packets - no need to increment + next buffer index since buffer was not used */ + break; + } + } + } + + /************************************************************************ + * + * MAC_AU1X00_write + * Description : + * ------------- + * This service requests transmission of a frame on the LAN interface. It is the caller's + * responsibility to fill in all information including the destination and source addresses and + * the frame type. The length parameter gives the number of bytes in the ethernet frame. + * The routine will not return until the frame has been transmitted or an error has occured. If + * the frame transmits successfully, OK is returned. If an error occured, a message is sent to + * the serial port and the routine returns non-zero. + * + * + * Parameters : + * ------------ + * + * 'major', IN, major device number + * 'minor', IN, minor device number for multi device drivers + * 'p_param', INOUT, LAN variable of type, t_LAN_IO_desc. + * + * + * Return values : + * --------------- + * + * 'OK'(=0) + * 'ERROR_LAN_COMM_ERROR': communication error detected + * + * + ************************************************************************/ + static + INT32 LAN_AU1X00_write( + UINT32 major, /* IN: major device number */ + UINT32 minor, /* IN: minor device number */ + t_LAN_IO_desc *p_param ) /* OUT: frame to transmit */ + { + UINT32 i; + UINT32 status, temp, x; + UINT8 *pbData = p_param->data ; + UINT32 dwLength = p_param->length ; + + UINT8 *pbPacketData; + UINT32 *pPacket ; + int BufferIndex; + t_MAC_AU1X00_device *pdevice ; + + if ( MAC_AU1X00_state == MAC_AU1X00_DRIVER_IS_STOPPED ) + { + + #ifdef ETH_DEBUG + printf("MAC_AU1X00_state is stopped"); + #endif + return( ERROR_LAN_TXM_ERROR ) ; + } + + #ifdef ETH_DEBUG + printf("MAC_AU1X00_Write"); + #endif + + /* get device context for this minor device */ + pdevice = &minor_device[minor] ; + + BufferIndex = (MACREG( pdevice->pAU1X00DMARegs, + SETV(DMA_TRANSMIT, MAC_DMA_TXRX) | + SETV(DMA_ADDRESS_EN,MAC_DMA_REG)) & + MAC_DMA_NEXTBUF_MASK) >> MAC_DMA_NEXTBUF; + + + pPacket = (UINT32*)KSEG1((pdevice->TxmBuffer[BufferIndex])); + + + if ( MACREG( pdevice->pAU1X00DMARegs, + SETV(DMA_TRANSMIT, MAC_DMA_TXRX) | + SETV(BufferIndex,MAC_DMA_BUF) | /* BufferIndex picks correct DMA register */ + SETV(DMA_ADDRESS_EN ,MAC_DMA_REG) ) + + & MAC_DMA_READY_MASK ) /* If either DONE or ENABLE are not 0 then DMA + channel is not ready */ + { + + + #ifdef ETH_DEBUG + printf("ERROR_LAN_NO_TXM_RESOURCES\n"); + #endif + return(ERROR_LAN_NO_TXM_RESOURCES); + } + + + pbPacketData = (UINT8* )pPacket ; + + /* copy the bits */ + memcpy( pbPacketData, pbData, dwLength); + pdevice->status.tx_bytes += dwLength; + pdevice->status.tx_packets++; + + + /* check to PAD packet up to minimum size */ + if (dwLength < MAC_AU1X00_MIN_PACKET_SIZE) + { + memset( (pbPacketData + dwLength), 0, (MAC_AU1X00_MIN_PACKET_SIZE-dwLength) ) ; + dwLength = MAC_AU1X00_MIN_PACKET_SIZE ; + } + + /* Set length register */ + + MACREG( pdevice->pAU1X00DMARegs, + SETV(DMA_TRANSMIT, MAC_DMA_TXRX) | + SETV(BufferIndex,MAC_DMA_BUF) | + SETV(DMA_LENGTH,MAC_DMA_REG) ) = dwLength; + + /* Enable Rx */ + + /* for (i=0; i< MAC_AU1X00_RX_BUFFERS ; i++) { + + MACREG( minor_device[minor].pAU1X00DMARegs, + SETV(DMA_RECEIVE, MAC_DMA_TXRX) | + SETV(i,MAC_DMA_BUF) | + SETV(DMA_ADDRESS_EN ,MAC_DMA_REG) ) + |= MAC_DMA_ENABLE_MASK; + } + + pdevice->NextRcvBufferIndex = (MACREG( pdevice->pAU1X00DMARegs, + SETV(DMA_RECEIVE, MAC_DMA_TXRX) | + SETV(DMA_ADDRESS_EN,MAC_DMA_REG)) & + MAC_DMA_NEXTBUF_MASK) >> MAC_DMA_NEXTBUF; + + + */ + + /* Enable DMA */ + MACREG( pdevice->pAU1X00DMARegs, + SETV(DMA_TRANSMIT, MAC_DMA_TXRX) | + SETV(BufferIndex,MAC_DMA_BUF) | /* i selects buffer */ + SETV(DMA_ADDRESS_EN ,MAC_DMA_REG) ) + = (pdevice->TxmBuffer[BufferIndex] & MAC_DMA_ADDR_MASK) | /* only upper 27 bits are used */ + SET(MAC_DMA_ENABLE); + + + + /* Now wait until either an error occurs or transmission completes successfully */ + i = 0 ; + while( 1 ) + { + /* check DMA Done bit */ + if ( MACREG( pdevice->pAU1X00DMARegs, + SETV(DMA_TRANSMIT, MAC_DMA_TXRX) | + SETV(BufferIndex,MAC_DMA_BUF) | + SETV(DMA_ADDRESS_EN,MAC_DMA_REG) ) & MAC_DMA_DONE_MASK) + { + + + status = MACREG( pdevice->pAU1X00DMARegs, + SETV(DMA_TRANSMIT, MAC_DMA_TXRX) | + SETV(BufferIndex,MAC_DMA_BUF) | + SETV(DMA_STATUS,MAC_DMA_REG) ); + + /* Clear Done bit */ + + MACREG( pdevice->pAU1X00DMARegs, + SETV(DMA_TRANSMIT, MAC_DMA_TXRX) | + SETV(BufferIndex,MAC_DMA_BUF) | + SETV(DMA_ADDRESS_EN,MAC_DMA_REG) ) + + &= ~MAC_DMA_DONE_MASK; + + #ifdef ETH_DEBUG + printf("Status = %08x\n", status); + #endif + + /* Check for frame abort */ + if (status & MAC_TRANSMIT_FA_MASK) + { + pdevice->status.tx_errors++; + + if (status & MAC_TRANSMIT_JT_MASK) + pdevice->status.tx_jt_errors++; + + if (status & MAC_TRANSMIT_NC_MASK) + pdevice->status.tx_nc_errors++; + + if (status & MAC_TRANSMIT_LS_MASK) + pdevice->status.tx_ls_errors++; + + if (status & MAC_TRANSMIT_ED_MASK) + pdevice->status.tx_ed_errors++; + + if (status & MAC_TRANSMIT_LC_MASK) + pdevice->status.tx_lc_errors++; + + if (status & MAC_TRANSMIT_EC_MASK) + pdevice->status.tx_lc_errors++; + else /* Collision Count is only valid if EC is not set */ + pdevice->status.collisions += + ((status & MAC_TRANSMIT_CC_MASK) >> MAC_TRANSMIT_CC) ; + + if (status & MAC_TRANSMIT_UR_MASK) + pdevice->status.tx_ur_errors++; + + } + + break ; + } + + i++ ; + + /* This corresponds to 1 second at 384MHz */ + + if ( i > 0x16e36000) + { + pdevice->status.tx_errors++; + pdevice->status.tx_timeout_errors++; + + /* re-init driver and controller */ + LAN_AU1X00_init( 0, 0, NULL ) ; + + return( ERROR_LAN_TXM_ERROR ) ; + } + } + + return( OK ) ; + } + + /************************************************************************ + * + * MAC_AU1X00_ctrl + * Description : + * ------------- + * This service requests special service via 'ctrl' + * + * + * Parameters : + * ------------ + * + * 'major', IN, major device number + * 'minor', IN, minor device number for multi device drivers + * 'p_param', INOUT, LAN variable of type, t_LAN_IO_desc. + * + * + * Return values : + * --------------- + * + * 'OK'(=0) + * + * + ************************************************************************/ + static + INT32 LAN_AU1X00_ctrl( + UINT32 major, /* IN: major device number */ + UINT32 minor, /* IN: minor device number */ + t_LAN_CTRL_desc *p_param ) /* IN-OUT: */ + { + t_MAC_AU1X00_device *pdevice ; + + /* get device context for this minor device */ + pdevice = &minor_device[minor] ; + + switch( p_param->command ) + { + case LAN_CTRL_DISPLAY_STATISTICS: + #ifdef ETH_DEBUG + MAC_AU1X00_dump_regs( pdevice ) ; + + /* The below was removed. May want to add a dump of current DMA pointers */ + /* MAC_AU1X00_dump_packetstatus( pdevice ) ; */ + #endif + MAC_AU1X00_MII_status( pdevice ) ; + MAC_AU1X00_dump_status( pdevice ) ; + break ; + + case LAN_CTRL_STOP_CONTROLLER: + MAC_AU1X00_stop( pdevice ) ; + break ; + + case LAN_CTRL_START_CONTROLLER: + /* re-init driver and controller */ + LAN_AU1X00_init( 0, 0, NULL ) ; + break ; + + default: + break ; + } + return( OK ) ; + } + + + /************************************************************************ + * + * MAC_AU1X00_dump_regs + * Description : + * ------------- + * Dump all AU1X00 LAN controller registers + * + * + * Parameters : + * ------------ + * + * 'pdevice', IN, reference for this device context + * + * + * Return values : + * --------------- + * + * 'OK'(=0) + * + * + * + ************************************************************************/ + static + INT32 MAC_AU1X00_dump_regs( t_MAC_AU1X00_device *pdevice ) + { + volatile void *pmac ; + + pmac = pdevice->pAU1X00CtrlRegs ; + + sprintf( msg, "\n\r MAC_AU1X00_dump_regs:\n\r") ; + PUTS( DEFAULT_PORT, msg ) ; + + sprintf( msg, "\n\r Control Base = %08x\n\r", (UINT32) pdevice->pAU1X00CtrlRegs) ; + PUTS( DEFAULT_PORT, msg ) ; + + sprintf( msg, " MAC_CONTROL: 0x%08X\n\r", MACREG(pmac, MAC_CONTROL) ) ; + PUTS( DEFAULT_PORT, msg ) ; + sprintf( msg, " MAC_ADDRHI: 0x%08X\n\r", MACREG(pmac, MAC_ADDRHI) ) ; + PUTS( DEFAULT_PORT, msg ) ; + sprintf( msg, " MAC_ADDRLO: 0x%08X\n\r", MACREG(pmac, MAC_ADDRLO) ) ; + PUTS( DEFAULT_PORT, msg ) ; + sprintf( msg, " MAC_MCHASHH: 0x%08X\n\r", MACREG(pmac, MAC_MCHASHH) ) ; + PUTS( DEFAULT_PORT, msg ) ; + sprintf( msg, " MAC_MCHASHL: 0x%08X\n\r", MACREG(pmac, MAC_MCHASHL) ) ; + PUTS( DEFAULT_PORT, msg ) ; + sprintf( msg, " MAC_MIICTRL: 0x%08X\n\r", MACREG(pmac, MAC_MIICTRL) ) ; + PUTS( DEFAULT_PORT, msg ) ; + sprintf( msg, " MAC_MIIDATA: 0x%08X\n\r", MACREG(pmac, MAC_MIIDATA) ) ; + PUTS( DEFAULT_PORT, msg ) ; + sprintf( msg, " MAC_FLOWCTL: 0x%08X\n\r", MACREG(pmac, MAC_FLOWCTL) ) ; + PUTS( DEFAULT_PORT, msg ) ; + sprintf( msg, " MAC_VLAN1TG: 0x%08X\n\r", MACREG(pmac, MAC_VLAN1TG) ) ; + PUTS( DEFAULT_PORT, msg ) ; + sprintf( msg, " MAC_VLAN2TG: 0x%08X\n\r", MACREG(pmac, MAC_VLAN2TG) ) ; + PUTS( DEFAULT_PORT, msg ) ; + + /* Revise: Need to add DMA registers here */ + + return( OK ) ; + } + + /************************************************************************ + * + * MAC_AU1X00_dump_status + * Description : + * ------------- + * Dump all AU1X00 LAN controller statistics + * + * + * Parameters : + * ------------ + * + * 'pdevice', IN, reference for this device context + * + * + * Return values : + * --------------- + * + * 'OK'(=0) + * + * + * + ************************************************************************/ + static + INT32 MAC_AU1X00_dump_status( t_MAC_AU1X00_device *pdevice ) + { + sprintf( msg, " Packets received: %ld\n\r", pdevice->status.rx_packets ) ; + PUTS( DEFAULT_PORT, msg ) ; + sprintf( msg, " Packets transmitted: %ld\n\r", pdevice->status.tx_packets ) ; + PUTS( DEFAULT_PORT, msg ) ; + sprintf( msg, " Bytes received: %ld\n\r", pdevice->status.rx_bytes ) ; + PUTS( DEFAULT_PORT, msg ) ; + sprintf( msg, " Bytes transmitted: %ld\n\r", pdevice->status.tx_bytes ) ; + PUTS( DEFAULT_PORT, msg ) ; + sprintf( msg, " Receive errors: %ld\n\r", pdevice->status.rx_errors ) ; + PUTS( DEFAULT_PORT, msg ) ; + sprintf( msg, " Transmit errors: %ld\n\r", pdevice->status.tx_errors ) ; + PUTS( DEFAULT_PORT, msg ) ; + sprintf( msg, " Multicasts received: %ld\n\r", pdevice->status.multicast ) ; + PUTS( DEFAULT_PORT, msg ) ; + sprintf( msg, " Collisions: %ld\n\r", pdevice->status.collisions) ; + PUTS( DEFAULT_PORT, msg ) ; + #ifdef ETH_DEBUG + sprintf( msg, " rx_zero_length_errors: %ld\n\r", pdevice->status.rx_zero_length_errors ) ; + PUTS( DEFAULT_PORT, msg ) ; + sprintf( msg, " rx_buffer_length_errors: %ld\n\r", pdevice->status.rx_buffer_length_errors) ; + PUTS( DEFAULT_PORT, msg ) ; + #endif + sprintf( msg, " Receive length errors: %ld\n\r", pdevice->status.rx_length_errors ) ; + PUTS( DEFAULT_PORT, msg ) ; + sprintf( msg, " Receive CRC errors: %ld\n\r", pdevice->status.rx_cr_errors ) ; + PUTS( DEFAULT_PORT, msg ) ; + sprintf( msg, " Receive Dribble errors: %ld\n\r", pdevice->status.rx_db_errors ) ; + PUTS( DEFAULT_PORT, msg ) ; + sprintf( msg, " Receive frame length: %ld\n\r", pdevice->status.rx_fl_errors ) ; + PUTS( DEFAULT_PORT, msg ) ; + sprintf( msg, " Transmit aborted errors: %ld\n\r", pdevice->status.tx_fa_errors) ; + PUTS( DEFAULT_PORT, msg ) ; + sprintf( msg, " Transmit lost carrier errors: %ld\n\r", pdevice->status.tx_ls_errors) ; + PUTS( DEFAULT_PORT, msg ) ; + sprintf( msg, " Transmit FIFO underrun errors: %ld\n\r", pdevice->status.tx_ur_errors) ; + PUTS( DEFAULT_PORT, msg ) ; + sprintf( msg, " Transmit late collision errors: %ld\n\r", pdevice->status.tx_lc_errors) ; + PUTS( DEFAULT_PORT, msg ) ; + sprintf( msg, " Transmit timeout errors: %ld\n\r", pdevice->status.tx_ed_errors) ; + PUTS( DEFAULT_PORT, msg ) ; + } ; + + + /************************************************************************ + * + * MAC_AU1X00_MII_status + * Description : + * ------------- + * Display MII status + * + * + * Parameters : + * ------------ + * + * 'pdevice', IN, reference for this device context + * + * + * Return values : + * --------------- + * + * 'OK'(=0) + * + * + * + ************************************************************************/ + static + INT32 MAC_AU1X00_MII_status( t_MAC_AU1X00_device *pdevice ) + { + UINT32 opmode ; + + /* check link status, spin here till done */ + while ( MACREG( pdevice->pAU1X00CtrlRegs, MAC_MIICTRL) & MAC_MIICTRL_MBUSY_MASK) ; + + /* set PHY address and read PHY Control register (This address is 0x00 so will + be read automatically */ + MACREG( pdevice->pAU1X00CtrlRegs, MAC_MIICTRL) = PHY_ADDRESS << MAC_MIICTRL_PHYA; + + /* check link status, spin here till done */ + while ( MACREG( pdevice->pAU1X00CtrlRegs, MAC_MIICTRL) & MAC_MIICTRL_MBUSY_MASK); + + /* check read register value */ + if ( MACREG( pdevice->pAU1X00CtrlRegs, MAC_MIIDATA) == PHY_CONTROL_DEFAULT) + { + sprintf( msg, " MII status: Link is up") ; + PUTS( DEFAULT_PORT, msg ) ; + } + else + { + /* link is down */ + sprintf( msg, " MII status: Link is down!" ) ; + PUTS( DEFAULT_PORT, msg ) ; + } + return(OK) ; + } diff -cNr yamon-sde6/drivers/rtc/rtc_au1x00.c yamon-devdrv/drivers/rtc/rtc_au1x00.c *** yamon-sde6/drivers/rtc/rtc_au1x00.c Thu Jan 1 09:00:00 1970 --- yamon-devdrv/drivers/rtc/rtc_au1x00.c Tue Sep 27 13:07:40 2005 *************** *** 0 **** --- 1,427 ---- + + /************************************************************************ + * + * rtc.c + * + * The 'RTC_AU1X00' module implements a device driver + * for Au1x00 TOY/RTC. + * + * IO services are handled the following way : + * + * 1) init serial device: configure and initialize RTC driver + * 2) open serial device: not used + * 3) close serial device: not used + * 4) read serial device: get RTC + * 5) write serial device: set RTC + * 6) ctrl serial device: not used + * + * ###################################################################### + * + * This program is largely copies by the RTC_AU1X00(made by AMD) + * source files. + * + * Copyright 2005 Device Drivers Limited. + * Author: kawamoto@devdrv.co.jp + * + ************************************************************************/ + + + + + /************************************************************************ + * Include files + ************************************************************************/ + + #include + #include + #include + #include + #include + #include + #include + #include + + /************************************************************************ + * Definitions + ************************************************************************/ + + + /************************************************************************ + * RTC device: Relative Register Addresses + ************************************************************************/ + + + /************************************************************************ + * Macro Definitions + *************************************************************************/ + + + /************************************************************************ + * Public variables + ************************************************************************/ + + + /************************************************************************ + * Static variables + ************************************************************************/ + + static UINT16 monthdays[13] = + { 0, 31, 59, 90, 120, 151, 181, 212, 243, 273, 304, 334, 365 }; + static UINT16 leapyeardays[13] = + { 0, 31, 60, 91, 121, 152, 182, 213, 244, 274, 305, 335, 366 }; + + /************************************************************************ + * Static function prototypes + ************************************************************************/ + + + /************************************************************************ + * + * RTC_init + * Description : + * ------------- + * This service initializes the RTC driver. + * + * + * Parameters : + * ------------ + * + * 'major', IN, major device number + * 'minor', IN, not used + * 'p_param', INOUT, not used + * + * + * Return values : + * --------------- + * + * 'OK'(=0) + * + * + * + ************************************************************************/ + static INT32 + RTC_AU1X00_init( + UINT32 major, /* IN: major device number */ + UINT32 minor, /* IN: minor device number */ + void *p_param ); /* INOUT: device parameter block */ + + + /************************************************************************ + * + * RTC_read + * Description : + * ------------- + * This service reads the current value of the Real Time Clock. + * + * + * Parameters : + * ------------ + * + * 'major', IN, major device number + * 'minor', IN, minor device number for multi device drivers + * 'p_param', INOUT, RTC variable of type, t_RTC_calendar. + * + * + * Return values : + * --------------- + * + * 'OK'(=0) + * + * + ************************************************************************/ + static INT32 + RTC_AU1X00_read( + UINT32 major, /* IN: major device number */ + UINT32 minor, /* IN: minor device number */ + t_RTC_calendar *p_param ); /* INOUT: current RTC value */ + + + /************************************************************************ + * + * RTC_write + * Description : + * ------------- + * This service sets the current value of the Real Time Clock. + * + * + * Parameters : + * ------------ + * + * 'major', IN, major device number + * 'minor', IN, minor device number for multi device drivers + * 'p_param', INOUT, RTC variable of type, t_RTC_calendar. + * + * + * Return values : + * --------------- + * + * 'OK'(=0) + * + * + ************************************************************************/ + static INT32 + RTC_AU1X00_write( + UINT32 major, /* IN: major device number */ + UINT32 minor, /* IN: minor device number */ + t_RTC_calendar *p_param ); /* INOUT: current RTC value */ + + + /************************************************************************ + * Implementation : Public functions + ************************************************************************/ + + + /************************************************************************ + * + * RTC_install + * Description : + * ------------- + * + * Installs the RTC device drivers services in the IO system + * at the reserved device slot, found in the 'sys_dev.h' file, + * which defines all major device numbers. + * + * Note: + * This service is the only public declared interface function; all + * provided device driver services are static declared, but this + * function installs the function pointers in the io-system to + * enable the provided public driver services. + * + * Parameters : + * ------------ + * + * None + * + * Return values : + * --------------- + * + * 'OK'(=0) + * 'ERROR_IO_ILLEGAL_MAJOR': Illegal major device number + * 'ERROR_IO_NO_SPACE': Device slot already allocated + * + ************************************************************************/ + INT32 + RTC_AU1X00_install( void ) + { + /* pre-initialize local variables and install device services */ + IO_install( SYS_MAJOR_RTC, /* major device number */ + (t_io_service) RTC_AU1X00_init, /* 'init' service */ + NULL, /* 'open' service N/A */ + NULL, /* 'close' service N/A */ + (t_io_service) RTC_AU1X00_read, /* 'read' service */ + (t_io_service) RTC_AU1X00_write, /* 'write' service */ + NULL ) ; /* 'ctrl' service N/A */ + + /* call our own 'init' service */ + return IO_init( SYS_MAJOR_RTC, 0, NULL); + } + + + + /************************************************************************ + * Implementation : Static functions + ************************************************************************/ + + /************************************************************************ + * + * RTC_init + * Description : + * ------------- + * This service initializes the RTC driver. + * + * + * Parameters : + * ------------ + * + * 'major', IN, major device number + * 'minor', IN, not used + * 'p_param', INOUT, not used + * + * + * Return values : + * --------------- + * + * 'OK'(=0) + * + * + * + ************************************************************************/ + static INT32 + RTC_AU1X00_init( + UINT32 major, /* IN: major device number */ + UINT32 minor, /* IN: minor device number */ + void *p_param ) /* INOUT: device parameter block */ + { + REG(KSEG1(AU1X00_SYS_BASE), AU1X00_SYS_CNTRCTRL) = 0x00000100; + + while((REG(KSEG1(AU1X00_SYS_BASE), AU1X00_SYS_CNTRCTRL) & 0x00000080)); + + while(!(REG(KSEG1(AU1X00_SYS_BASE), AU1X00_SYS_CNTRCTRL) & 0x00000020)); + + REG(KSEG1(AU1X00_SYS_BASE), AU1X00_SYS_TOYTRIM) = 0x00007FFF; + + return( OK ); + } + + + /************************************************************************ + * + * RTC_read + * Description : + * ------------- + * This service reads the current value of the Real Time Clock. + * + * + * Parameters : + * ------------ + * + * 'major', IN, major device number + * 'minor', IN, minor device number for multi device drivers + * 'p_param', INOUT, RTC variable of type, t_RTC_calendar. + * + * + * Return values : + * --------------- + * + * 'OK'(=0) + * + * + ************************************************************************/ + static INT32 + RTC_AU1X00_read( + UINT32 major, /* IN: major device number */ + UINT32 minor, /* IN: minor device number */ + t_RTC_calendar *p_param ) /* INOUT: current RTC value */ + { + UINT32 TOY_value; + UINT32 year; + UINT32 month = 1; + INT32 days; + bool leapyear; + UINT32 i; + + TOY_value = REG(KSEG1(AU1X00_SYS_BASE), AU1X00_SYS_TOYREAD); + + days = TOY_value/(60 * 60 * 24); + p_param->hour = (TOY_value - (days * 60 * 60 * 24)) / (60 * 60); + p_param->minute = (TOY_value - (days * 60 * 60 * 24) - (p_param->hour * 60 * 60)) / 60; + p_param->second = TOY_value - (days * 60 * 60 * 24) - (p_param->hour * 60 * 60) - (p_param->minute * 60); + year = 2000; + + while(days>365) + { + leapyear= ((year % 4) == 0 && ((year % 100) != 0 || (year % 400) == 0)); + if(leapyear && days > 366) + { + year++; + days -= 366; + } + else if (!leapyear && days > 365) + { + year++; + days -= 365; + } + else + break; + } + leapyear= ((year % 4) == 0 && ((year % 100) != 0 || (year % 400) == 0)); + + if(leapyear) + while(days > leapyeardays[month]) + month++; + else + while(days > monthdays[month]) + month++; + + if(leapyear) + p_param->dayofmonth = days - leapyeardays[month - 1]; + else + p_param->dayofmonth = days - monthdays[month - 1]; + + year--; + days = year*365 + year/4 - year/100 + year/400; + year++; + + if (leapyear) + days += leapyeardays[month-1]; + else + days += monthdays[month-1]; + + days += p_param->dayofmonth; + p_param->dayofweek = days % 7; + p_param->dayofweek++; + p_param->month = month; + p_param->year = year; + + return( OK ); + } + + + /************************************************************************ + * + * RTC_write + * Description : + * ------------- + * This service sets the current value of the Real Time Clock. + * + * + * Parameters : + * ------------ + * + * 'major', IN, major device number + * 'minor', IN, minor device number for multi device drivers + * 'p_param', INOUT, RTC variable of type, t_RTC_calendar. + * + * + * Return values : + * --------------- + * + * 'OK'(=0) + * + * + ************************************************************************/ + static INT32 + RTC_AU1X00_write( + UINT32 major, /* IN: major device number */ + UINT32 minor, /* IN: minor device number */ + t_RTC_calendar *p_param ) /* INOUT: current RTC value */ + { + + UINT32 year; + UINT32 days; + UINT32 seconds; + bool leapyear; + UINT32 i; + + year = p_param->year; + leapyear = ((year % 4) == 0 && ((year % 100) != 0 || (year % 400) == 0)); + + year = year - 2000; + + i = p_param->year - 2000; + days = 0; + while(i) + { + i--; + days += ((i % 4) == 0 && ((i % 100) != 0 || (i % 400) == 0)) ? 366 : 365; + } + + if(leapyear) + days += leapyeardays[p_param->month - 1]; + else + days += monthdays[p_param->month - 1]; + + days += p_param->dayofmonth; + + seconds = days * 24 * 60 * 60; + + seconds += (p_param->hour * 60 * 60) + (p_param->minute * 60) + p_param->second; + + while(REG(KSEG1(AU1X00_SYS_BASE), AU1X00_SYS_CNTRCTRL) & 0x00000001); + + REG(KSEG1(AU1X00_SYS_BASE), AU1X00_SYS_TOYWRITE) = seconds; + + while(REG(KSEG1(AU1X00_SYS_BASE), AU1X00_SYS_CNTRCTRL) & 0x00000001); + + return( OK ); + } diff -cNr yamon-sde6/drivers/serial/serial_au1x00.c yamon-devdrv/drivers/serial/serial_au1x00.c *** yamon-sde6/drivers/serial/serial_au1x00.c Thu Jan 1 09:00:00 1970 --- yamon-devdrv/drivers/serial/serial_au1x00.c Thu Sep 22 14:52:16 2005 *************** *** 0 **** --- 1,981 ---- + + /************************************************************************ + * + * SERIAL_AU1X00.c + * + * The 'SERIAL_AU1X00' module implements the SERIAL-AU1X00 + * device driver as an IO device with following services: + * + * 1) init device: configure and initialize serial driver + * 2) open device: not used + * 3) close device: not used + * 4) read device: read character from serial device + * 5) write device: write character to serial device + * 6) ctrl device: statistics and poll for ctrl/c + * + * + * ###################################################################### + * + * This program is largely copies by the SERIAL_TI16550 source files. + * + * Copyright 2005 Device Drivers Limited. + * Author: kawamoto@devdrv.co.jp + * + ************************************************************************/ + + + /************************************************************************ + * Include files + ************************************************************************/ + + #include + #include + #include + #include + #include + #include + #include + #include + #include + #include + + + + /************************************************************************ + * Definitions + *************************************************************************/ + + #define SET_ADDR( offset ) (void *)( au1x00base + offset ) + + + /* Register access */ + + #define PHY_THR_W(minor, data) *(phy_thr[minor]) = (data); + #define PHY_IER_W(minor, data) *(phy_ier[minor]) = (data); + #define PHY_FCR_W(minor, data) *(phy_fcr[minor]) = (data); + #define PHY_LCR_W(minor, data) *(phy_lcr[minor]) = (data); + #define PHY_MCR_W(minor, data) *(phy_mcr[minor]) = (data); + #define PHY_UCD_W(minor, data) *(phy_ucd[minor]) = (data); + #define PHY_UBC_W(minor, data) *(phy_ubc[minor]) = (data); + + + #define PHY_RBR_R(minor) ( *(phy_rbr[minor]) ) + #define PHY_LSR_R(minor) ( *(phy_lsr[minor]) ) + #define PHY_MSR_R(minor) ( *(phy_msr[minor]) ) + + /************************************************************************ + * Public variables + ************************************************************************/ + + + /************************************************************************ + * Static variables + ************************************************************************/ + + /* Base address of controller */ + static void *au1x00base; + + static volatile UINT32 *phy_rbr[SERIAL_MAX_AU1X00_DEVICES]; /* RO, receive buffer, */ + static volatile UINT32 *phy_thr[SERIAL_MAX_AU1X00_DEVICES]; /* WO, trans. holding, */ + static volatile UINT32 *phy_ier[SERIAL_MAX_AU1X00_DEVICES]; /* RW, int. enable, */ + static volatile UINT32 *phy_iir[SERIAL_MAX_AU1X00_DEVICES]; /* RO, int. ident, */ + static volatile UINT32 *phy_fcr[SERIAL_MAX_AU1X00_DEVICES]; /* WO, FIFO control, */ + static volatile UINT32 *phy_lcr[SERIAL_MAX_AU1X00_DEVICES]; /* RW, line control, */ + static volatile UINT32 *phy_mcr[SERIAL_MAX_AU1X00_DEVICES]; /* RW, modem control, */ + static volatile UINT32 *phy_lsr[SERIAL_MAX_AU1X00_DEVICES]; /* RW, line status, */ + static volatile UINT32 *phy_msr[SERIAL_MAX_AU1X00_DEVICES]; /* RW, modem status, */ + static volatile UINT32 *phy_ucd[SERIAL_MAX_AU1X00_DEVICES]; /* RW, clock divisor */ + static volatile UINT32 *phy_ubc[SERIAL_MAX_AU1X00_DEVICES]; /* RW, modem block control */ + + + /* Databit conversion table. + * EEPROM-encoding to device control + */ + static const UINT8 serial_databits[SERIAL_DATABITS_MAX] = { + + SERIAL_ILLEGAL, /* 0, undefined */ + SERIAL_LCR_DATA7, /* 1, 7 databits */ + SERIAL_LCR_DATA8 /* 2, 8 databits */ + }; + + + /* Parity conversion table. + * EEPROM-encoding to device control + */ + static const UINT8 serial_parity[SERIAL_PARITY_MAX] = { + + SERIAL_ILLEGAL, /* 0, undefined */ + SERIAL_LCR_PARITYNONE, /* 1, none */ + SERIAL_LCR_PARITYODD, /* 2, odd */ + SERIAL_LCR_PARITYEVEN /* 3, even */ + }; + + + /* Stopbits conversion table. + * EEPROM-encoding to device control + */ + static const UINT8 serial_stopbits[SERIAL_STOPBITS_MAX] = { + + SERIAL_ILLEGAL, /* 0, undefined */ + SERIAL_LCR_STOP1, /* 1, 1 stopbit */ + SERIAL_LCR_STOP15, /* 2, 1.5 stopbit */ + SERIAL_LCR_STOP2 /* 3, 2 stopbit */ + + }; + + static t_UART_statistics uart_statistics[SERIAL_MAX_AU1X00_DEVICES]; + static UINT32 poll_retcode[SERIAL_MAX_AU1X00_DEVICES]; + static UINT32 shadow_ier[SERIAL_MAX_AU1X00_DEVICES]; + static UINT32 shadow_mcr[SERIAL_MAX_AU1X00_DEVICES]; + static UINT32 shadow_flow[SERIAL_MAX_AU1X00_DEVICES]; + + + /* Receive buffer operation: + * + * putptr points to the next free location + * When a byte is polled from the uart, it is stored by putptr, + * which is then cyclic incremented UNLESS it gets equal to getptr. + * + * That way, getptr == putptr means buffer empty, and + * the buffer can hold POLLSIZE-1 bytes. + */ + + #define POLLSIZE 0x800 /* Must be power of 2 and at least 128 */ + #define HW_LIMIT_STOP (POLLSIZE-64) /* RTS OFF when 64 chars in buf */ + #define HW_LIMIT_START (POLLSIZE-32) /* RTS ON when 32 chars in buf */ + + static UINT16 *recv_putptr[SERIAL_MAX_AU1X00_DEVICES]; + static UINT16 *recv_getptr[SERIAL_MAX_AU1X00_DEVICES]; + static UINT16 *recv_flushptr[SERIAL_MAX_AU1X00_DEVICES]; + static UINT16 recv_buffer[SERIAL_MAX_AU1X00_DEVICES][POLLSIZE]; + + static UINT32 minor_numbers[SERIAL_MAX_AU1X00_DEVICES]; + + /* Available baudrates */ + static t_SERIAL_baudrate_div *serial_baudrate; + + /* Boolean indicating whether interrupt handlers are registered or not. + * Initial value is 0 (FALSE) since data is in BSS. + */ + static bool registered[SERIAL_MAX_AU1X00_DEVICES]; + + /* reverse-lookup table from t_SERIAL_baudrate_ids back to integer bps rates */ + /* (this must match up with indexes to t_SERIAL_baudrate_ids typedef.) */ + static UINT32 SERIAL_baudrate_rates[] = + { + 0, + 75, + 110, + 150, + 300, + 600, + 1200, + 1800, + 2400, + 4800, + 7200, + 9600, + 14400, + 19200, + 38400, + 57600, + 115200, + 230400, + 460800, + 921600 + }; + + /************************************************************************ + * Static function prototypes + ************************************************************************/ + + static INT32 + SERIAL_AU1X00_init( + UINT32 major, /* IN: major device number */ + UINT32 minor, /* IN: minor device number */ + UINT32 *port ); /* IN: port mapping */ + + static INT32 + SERIAL_AU1X00_read( + UINT32 major, /* IN: major device number */ + UINT32 minor, /* IN: minor device number */ + UINT8 *p_param ); /* OUT: character been read */ + + static UINT32 + SERIAL_AU1X00_irqpoll( + UINT32 minor ); + + static UINT32 + SERIAL_AU1X00_irq( + UINT32 minor, + UINT32 in_intrpt ); + + static INT32 + SERIAL_AU1X00_write( + UINT32 major, /* IN: major device number */ + UINT32 minor, /* IN: minor device number */ + UINT8 *p_param ); /* IN: character to write */ + + static INT32 + SERIAL_AU1X00_ctrl( + UINT32 major, /* IN: major device number */ + UINT32 minor, /* IN: minor device number */ + t_SERIAL_ctrl_descriptor *p_param );/* INOUT: IOCTL structure */ + + static void + serial_int_handler( + void *data ); /* Holds the minor device number */ + + + /************************************************************************ + * Implementation : Public functions + ************************************************************************/ + + + /************************************************************************ + * + * SERIAL_AU1X00_install + * Description : + * ------------- + * + * Installs the serial AU1X00 serial device drivers services in + * the IO system at the reserved device slot, found in the + * 'sysdev.h' file, which defines all major device numbers. + * + * Note: + * This service is the only public declared interface function; all + * provided device driver services are static declared, but this + * function installs the function pointers in the io-system to + * enable the provided public driver services. + * + * Parameters : + * ------------ + * + * None + * + * Return values : + * --------------- + * + * 'OK'(=0) + * 'ERROR_IO_ILLEGAL_MAJOR': Illegal major device number + * 'ERROR_IO_NO_SPACE': Device slot already allocated + * + ************************************************************************/ + INT32 + SERIAL_AU1X00_install( void ) + { + UINT32 i; + UINT32 tty; + UINT32 major, minor; + + + /* Initialise variables */ + for( i=0; i= SERIAL_BAUDRATE_MAX || + (*serial_baudrate)[baudrate] == SERIAL_ILLEGAL ) + { + return( ERROR_SERIAL_INVALID_BAUDRATE ) ; + } + + if (databits >= SERIAL_DATABITS_MAX || + serial_databits[databits] == SERIAL_ILLEGAL ) + { + return( ERROR_SERIAL_INVALID_DATABITS ) ; + } + + if (parity >= SERIAL_PARITY_MAX || + serial_parity[parity] == SERIAL_ILLEGAL ) + { + return( ERROR_SERIAL_INVALID_PARITY ) ; + } + + if (stopbits >= SERIAL_STOPBITS_MAX || + serial_stopbits[stopbits] == SERIAL_ILLEGAL ) + { + return( ERROR_SERIAL_INVALID_STOPBITS ) ; + } + + if (flowctrl >= SERIAL_FLOWCTRL_MAX || + flowctrl == SERIAL_FLOWCTRL_NOT_DEFINED ) + { + return( ERROR_SERIAL_INVALID_FLOWCTRL ) ; + } + + + /* convert */ + databits = serial_databits[databits]; + parity = serial_parity[parity]; + stopbits = serial_stopbits[stopbits]; + bps_raw = SERIAL_baudrate_rates[baudrate]; + SYSCON_read(SYSCON_BOARD_CPU_CLOCK_FREQ_ID, &cpu_speed, sizeof(cpu_speed)); + SYSCON_read(SYSCON_BOARD_BUS_CLOCK_FREQ_ID, &sys_speed, sizeof(sys_speed)); + sysbusdiv = cpu_speed / sys_speed; + den_temp = 2 * 16 * sysbusdiv * bps_raw; + clkdiv = ((cpu_speed % den_temp) > (den_temp / 2)) + ? (cpu_speed / den_temp + 1) + : (cpu_speed / den_temp); + + /* initialize physical register addresses based */ + phy_rbr[minor] = SET_ADDR( AU1X00_UART_RXDATA_OFS ); + phy_thr[minor] = SET_ADDR( AU1X00_UART_TXDATA_OFS ); + phy_ier[minor] = SET_ADDR( AU1X00_UART_INTEN_OFS ); + phy_iir[minor] = SET_ADDR( AU1X00_UART_INTCAUSE_OFS ); + phy_fcr[minor] = SET_ADDR( AU1X00_UART_FIFOCTRL_OFS ); + phy_lcr[minor] = SET_ADDR( AU1X00_UART_LINECTRL_OFS ); + phy_mcr[minor] = SET_ADDR( AU1X00_UART_MDMCTRL_OFS ); + phy_lsr[minor] = SET_ADDR( AU1X00_UART_LINESTAT_OFS ); + phy_msr[minor] = SET_ADDR( AU1X00_UART_MDMSTAT_OFS ); + phy_ucd[minor] = SET_ADDR( AU1X00_UART_CLKDIV_OFS ); + phy_ubc[minor] = SET_ADDR( AU1X00_UART_ENABLE_OFS ); + + /* Enable Clocks */ + PHY_UBC_W(minor, SERIAL_UBC_CE); + + /* bring out of reset with clocks enabled */ + PHY_UBC_W(minor, SERIAL_UBC_CE | SERIAL_UBC_ME); + + /* init IER: clear all interrupts */ + PHY_IER_W(minor, 0); + shadow_ier[minor] = 0; + + /* initalize poll buffer pointers */ + recv_getptr[minor] = recv_putptr[minor] = &recv_buffer[minor][0]; + + /* clear statistical info */ + uart_statistics[minor].ua_tx_bytes = 0; + uart_statistics[minor].ua_rx_bytes = 0; + uart_statistics[minor].ua_rx_overrun = 0; + uart_statistics[minor].ua_rx_parity = 0; + uart_statistics[minor].ua_rx_framing = 0; + uart_statistics[minor].ua_rx_break = 0; + uart_statistics[minor].ua_rx_irqs = 0; + uart_statistics[minor].ua_no_of_init++; + + /* Init baudrate : + * 1) enable DL-registers + * 2) set DLL + DLM divisor registers + * 3) disable DL-registers + */ + PHY_UCD_W(minor, clkdiv); + + /* Init LCR: + * 1) 8-bit data + * 2) 1 stop bit + * 3) no parity + */ + PHY_LCR_W(minor, databits | stopbits | parity); + + /* Init FCR: + * 1) enable FIFO + * 2) reset receiver FIFO + * 3) reset transmitter FIFO + * 4) set receive FIFO threshold to 4 + */ + PHY_FCR_W(minor, SERIAL_FCR_ENABLE | + SERIAL_FCR_RCVR_RESET | + SERIAL_FCR_TXMT_RESET | + SERIAL_FCR_RCVFIFO_4); + + /* Init MCR: + * 1) set DTR + * 2) set RTS + * 3) enable auto-flow control (both RX and TX) + * (Texas only; SuperIO and Philips: No OPeration) + * 4) enable interrupt mask (OUT2) + * (SuperIO and Philips only; Texas: NC on Atlas,SEAD,Malta) + */ + shadow_flow[minor] = flowctrl == SERIAL_FLOWCTRL_HARDWARE ? SERIAL_MCR_AFE : 0; + shadow_mcr[minor] = shadow_flow[minor] | + SERIAL_MCR_DTR | + SERIAL_MCR_RTS | + SERIAL_MCR_OUT2; + PHY_MCR_W(minor, shadow_mcr[minor]); + + + if( adjust_break ) + { + /* limit BRKRES register to prevent low baudrates from forcing reset */ + rcode = SYSCON_read( SYSCON_BOARD_BRKRES_ID, &brkresval, sizeof(brkresval)); + + if(rcode == OK && brkresval && brkresval < (*serial_baudrate)[baudrate]>>4) + { + brkresval = (*serial_baudrate)[baudrate] >> 4; + + rcode = SYSCON_write( SYSCON_BOARD_BRKRES_ID, + &brkresval, + sizeof(brkresval)); + } + } + + /* If this is the first call of init, we need to install interrupt handler */ + if( !registered[minor] ) + { + /* Determine parameter for interrupt service routine */ + minor_data = (void *)&minor_numbers[minor]; + + /* Register interrupt handler */ + if( ic_in_use ) + { + EXCEP_register_ic_isr( int_line, + serial_int_handler, + minor_data, + NULL ); + } + else + { + EXCEP_register_cpu_isr( int_line, + serial_int_handler, + minor_data, + NULL ); + } + + registered[minor] = TRUE; + } + + /* Configure driver to be interrupt driven */ + ctrl.sc_command = SERIAL_CTRL_RCV_IRQ_ON; + SERIAL_AU1X00_ctrl( major, minor, &ctrl ); + + return( OK ); + } + + + /************************************************************************ + * serial_int_handler + ************************************************************************/ + static void + serial_int_handler( + void *data ) /* Holds the minor device number */ + { + t_SERIAL_ctrl_descriptor ctrl; + + ctrl.sc_command = SERIAL_CTRL_RCV_IRQ; + + SERIAL_AU1X00_ctrl( 0, *(UINT32 *)data, &ctrl ); + } + + + /************************************************************************ + * + * SERIAL_AU1X00_read + * Description : + * ------------- + * This service polls the specified channel for any present character. + * If any character is present, it will be read into the user allocated + * variable; if none present, completion = 'ERROR_SERIAL_NO_CHARACTER' + * will be returned. + * + * Parameters : + * ------------ + * + * 'major', IN, major device number + * 'minor', IN, minor device number for multi device drivers + * 'p_param', OUT, character read + * + * Return values : + * --------------- + * 'OK' = 0x00: character read into user variable + * 'ERROR_SERIAL_NO_CHARACTER': no character present on channel + * 'ERROR_SERIAL_COMM_ERROR': communication error detected + * 'ERROR_SERIAL_COMM_BREAK': 'BREAK' detected + * + ************************************************************************/ + static INT32 + SERIAL_AU1X00_read( + UINT32 major, /* IN: major device number */ + UINT32 minor, /* IN: minor device number */ + UINT8 *p_param ) /* OUT: character been read */ + { + UINT32 rc; + UINT32 lstat; + UINT16 *getptr; + + /* check minor device number */ + if(minor >= SERIAL_MAX_AU1X00_DEVICES) + { + return(ERROR_SERIAL_UNKNOWN_DEVICE); + } + + /* check for device initialization */ + if( phy_lsr[minor] == NULL ) + { + return( ERROR_SERIAL_UNKNOWN_DEVICE ); + } + + SERIAL_AU1X00_irqpoll( minor ); /* service UART */ + + getptr= recv_getptr[minor]; + if (getptr == recv_putptr[minor]) + return( ERROR_SERIAL_NO_CHARACTER ); + + if (poll_retcode[minor] != OK) + { + poll_retcode[minor] = OK; + /* flush receive buffer up to the last received ctrl/c or break */ + getptr = recv_flushptr[minor]; + + /* always read CTRL/C in case of 'break' or ctrl/c */ + lstat = (*getptr & 0xff00) | CTRL_C; + + rc = ERROR_SERIAL_COMM_BREAK; + } + else + { + lstat = *getptr; + rc = OK; + } + + *p_param = lstat; + uart_statistics[minor].ua_rx_bytes++; + + /* check for errors */ + if (lstat & ((SERIAL_LSR_OE<<8) | + (SERIAL_LSR_PE<<8) | + (SERIAL_LSR_FE<<8))) + { + if (rc == OK) rc = ERROR_SERIAL_COMM_ERROR ; + if (lstat & (SERIAL_LSR_OE<<8)) uart_statistics[minor].ua_rx_overrun++; + if (lstat & (SERIAL_LSR_PE<<8)) uart_statistics[minor].ua_rx_parity++; + if (lstat & (SERIAL_LSR_FE<<8)) uart_statistics[minor].ua_rx_framing++; + } + + if (++getptr >= &recv_buffer[minor][POLLSIZE]) + getptr= &recv_buffer[minor][0]; + recv_getptr[minor] = getptr; + + /* compute room in buffer */ + if ( (shadow_mcr[minor] & SERIAL_MCR_RTS) == 0 && + (((UINT32)getptr - (UINT32)recv_putptr[minor]) & + ((POLLSIZE - 1) * sizeof(*getptr))) + >= HW_LIMIT_START * sizeof(*getptr) ) + { + shadow_mcr[minor] |= SERIAL_MCR_RTS; + PHY_MCR_W(minor, shadow_mcr[minor]); + } + + return( rc ); + } + + + /************************************************************************ + * + * SERIAL_AU1X00_irqpoll + * Description : + * ------------- + * Disabling of interrupts around call of SERIAL_AU1X00_irq() + * + ************************************************************************/ + static UINT32 + SERIAL_AU1X00_irqpoll( + UINT32 minor ) + { + UINT32 lstat; + + if(sys_disable_int()) + { + lstat = SERIAL_AU1X00_irq( minor, 0 ); + sys_enable_int(); + } + else + lstat = SERIAL_AU1X00_irq( minor, 0 ); + + return lstat; + } + + + /************************************************************************ + * + * SERIAL_AU1X00_irq + * Description : + * ------------- + * This service empties the UART's FIFO buffer and puts the chars into + * the cyclic receive buffer. + * + * This routine is called in both polled and interrupt mode. + * and requires interrupts to be disabled. + * + * static variables written: + * poll_retcode BREAK or CTRL/C has been read + * recv_putptr2 pointer to next free position in cyclic queue. + * + * static variables read: + * phy_lsr pointer to UART line status register + * phy_rbr pointer to UART receive data register + * recv_getptr pointer to first unread position in cyclic queue. + * recv_flushptr pointer to position of last read break or ctrl/c + * + ************************************************************************/ + static UINT32 + SERIAL_AU1X00_irq( + UINT32 minor, + UINT32 in_intrpt ) + { + UINT32 lstat; /* LSR_OE, LSR_PE, LSR_FE and LSR_BI are clear on read */ + UINT8 rdata; + UINT16 *putptr; + UINT32 room; + + putptr = recv_putptr[minor]; + + /* empty FIFO */ + for(lstat = PHY_LSR_R(minor); lstat & SERIAL_LSR_DR; lstat = PHY_LSR_R(minor)) + { + rdata = PHY_RBR_R(minor) & 0xff; + uart_statistics[minor].ua_rx_irqs += in_intrpt; + + if(lstat & SERIAL_LSR_BI) + { + rdata = CTRL_C; + uart_statistics[minor].ua_rx_break++; + } + + /* compute room left in buffer, AFTER this byte has been put */ + room = ((UINT32)recv_getptr[minor] - (UINT32)putptr - 1) & + ((POLLSIZE - 1) * sizeof(*putptr)); + + if (room <= HW_LIMIT_STOP * sizeof(*putptr) && shadow_flow[minor] != 0) + { + shadow_mcr[minor] &= ~SERIAL_MCR_RTS; + PHY_MCR_W(minor, shadow_mcr[minor]); + } + + if(room == 0) + { + lstat |= SERIAL_LSR_OE; /* overrun */ + /* overwrite previous char (overflow anyway) */ + if (--putptr < &recv_buffer[minor][0]) + putptr= &recv_buffer[minor][POLLSIZE-1]; + } + + *putptr = (lstat << 8) | rdata; + + if(rdata == CTRL_C) + { + poll_retcode[minor] = ERROR_SERIAL_COMM_BREAK; + recv_flushptr[minor] = putptr; + } + + /* increase putptr to its future position */ + if( ++putptr >= &recv_buffer[minor][POLLSIZE] ) + putptr= &recv_buffer[minor][0]; + } + + recv_putptr[minor] = putptr; + return lstat; + } + + + /************************************************************************ + * + * SERIAL_AU1X00_write + * Description : + * ------------- + * This service writes a character on the specified channel + * + * Parameters : + * ------------ + * + * 'major', IN, major device number + * 'minor', IN, minor device number for multi device drivers + * 'p_param', IN, pointer to character to write + * + * Return values : + * --------------- + * 'OK' = 0x00: character has been written on channel + * + ************************************************************************/ + static INT32 + SERIAL_AU1X00_write( + UINT32 major, /* IN: major device number */ + UINT32 minor, /* IN: minor device number */ + UINT8 *p_param ) /* IN: pointer to character to write */ + { + + /* check minor device number */ + if(minor >= SERIAL_MAX_AU1X00_DEVICES) + { + return(ERROR_SERIAL_UNKNOWN_DEVICE); + } + + /* check for device initialization */ + if( phy_lsr[minor] == NULL ) + { + return( ERROR_SERIAL_UNKNOWN_DEVICE ); + } + + /* check line status and modem status */ + for (;;) + { + /* OBS: LSR_OE, LSR_PE, LSR_FE and LSR_BI are cleared on read */ + if ( (SERIAL_AU1X00_irqpoll( minor ) & SERIAL_LSR_THRE) && + ((PHY_MSR_R(minor) & SERIAL_MSR_CTS) || shadow_flow[minor] == 0)) break; + } + + /* write character */ + PHY_THR_W(minor, *p_param); + uart_statistics[minor].ua_tx_bytes++; + + return( OK ); + } + + + /************************************************************************ + * + * SERIAL_AU1X00_ctrl + * Description : + * ------------- + * This service performs the actions defined by t_SERIAL_ctrl_command_ids + * on the specified channel. + * + * Parameters : + * ------------ + * + * 'major', IN, major device number + * 'minor', IN, minor device number for multi device drivers + * 'p_param', INOUT, IOCTL structure + * + * Return values : + * --------------- + * 'OK' = 0x00: normal return + * ERROR_SERIAL_COMM_BREAK: break or ctrl/c received + * ERROR_SERIAL_COMM_ERROR: receive error, characters lost + * + ************************************************************************/ + static INT32 + SERIAL_AU1X00_ctrl( + UINT32 major, /* IN: major device number */ + UINT32 minor, /* IN: minor device number */ + t_SERIAL_ctrl_descriptor *p_param ) /* INOUT: IOCTL structure */ + { + UINT32 rcode; + + /* check minor device number */ + if(minor >= SERIAL_MAX_AU1X00_DEVICES) + { + return(ERROR_SERIAL_UNKNOWN_DEVICE); + } + + /* check for device initialization */ + if( phy_lsr[minor] == NULL ) + { + return( ERROR_SERIAL_UNKNOWN_DEVICE ); + } + + if(p_param == NULL) + { + return( ERROR_SERIAL_INVALID_ARGUMENT ); + } + + rcode = OK; + switch( p_param->sc_command ) + { + case SERIAL_CTRL_POLL_BREAK: + SERIAL_AU1X00_irqpoll(minor); /* service UART */ + if( (rcode = poll_retcode[minor]) != OK ) + { + /* flush read buffer */ + rcode = SERIAL_AU1X00_read( major, minor, (UINT8 *)&rcode ); + } + break; + + case SERIAL_CTRL_GET_STATISTICS: + memcpy((UINT8*)&p_param->sc_arg.sc_statistics, + (UINT8 *)&uart_statistics[minor], + sizeof(uart_statistics[minor])); + break; + + case SERIAL_CTRL_GET_LSR: + p_param->sc_arg.sc_linestat = SERIAL_AU1X00_irqpoll( minor ); + break; + + case SERIAL_CTRL_RCV_IRQ: + SERIAL_AU1X00_irq( minor, 1 ); + break ; + + case SERIAL_CTRL_RCV_IRQ_ON: + PHY_IER_W(minor, SERIAL_IER_RCVEN); + shadow_ier[minor] = SERIAL_IER_RCVEN; + break ; + + case SERIAL_CTRL_RCV_IRQ_OFF: + shadow_ier[minor] = 0; + PHY_IER_W(minor, 0); + break; + + case SERIAL_CTRL_FORCE_DTR: + if (p_param->sc_arg.sc_dtr == 0) + shadow_mcr[minor] &= ~SERIAL_MCR_DTR; + else + shadow_mcr[minor] |= SERIAL_MCR_DTR; + PHY_MCR_W(minor, shadow_mcr[minor]); + break; + + case SERIAL_CTRL_GET_MSR: + p_param->sc_arg.sc_msr = PHY_MSR_R(minor); + break; + + case SERIAL_CTRL_SEND_BREAK: + *(phy_lcr[minor]) |= SERIAL_LCR_BREAK; + sys_wait_ms(250); + *(phy_lcr[minor]) &= ~SERIAL_LCR_BREAK; + break; + + default: + rcode = ERROR_SERIAL_INVALID_ARGUMENT; + } + + return( rcode ); + } + + + diff -cNr yamon-sde6/include/flash_amd_api.h yamon-devdrv/include/flash_amd_api.h *** yamon-sde6/include/flash_amd_api.h Thu Jan 1 09:00:00 1970 --- yamon-devdrv/include/flash_amd_api.h Fri Aug 12 13:58:46 2005 *************** *** 0 **** --- 1,76 ---- + #ifndef FLASH_AMD_API_H + #define FLASH_AMD_API_H + + /************************************************************************ + * + * FLASH_STRATA_api.h + * + * The 'FLASH_STRATA_api' module defines the specific public + * interface for the Intel STRATA FLASH device driver. The + * generic FLASH device driver interface is defined in the + * 'flash_api' module, which is supported by this driver. + * + * The specific public interface comprise: + * + * 1) FLASH_STRATA_install: installs the 'FLASH' device driver + * services into the 'io' system. + * + * + * + * ###################################################################### + * + * This program is largely copies by the FLASH_STRATA source files. + * + * Copyright 2005 Device Drivers Limited. + * Author: kawamoto@devdrv.co.jp + * + ************************************************************************/ + + + + + /************************************************************************ + * Include files + ************************************************************************/ + + #include "sysdefs.h" + + + /************************************************************************ + * Public functions + ************************************************************************/ + + /************************************************************************ + * + * FLASH_STRATA_install + * Description : + * ------------- + * + * Installs the serial STRATA FLASH device drivers services in + * the IO system at the reserved device slot, found in the + * 'sys_dev.h' file, which defines all major device numbers. + * + * Note: + * This service is the only public declared interface function; all + * provided device driver services are static declared, but this + * function installs the function pointers in the io-system to + * enable the provided public driver services. + * + * Parameters : + * ------------ + * + * - + * + * + * Return values : + * --------------- + * + * 'OK'(=0) + * 'ERROR_IO_ILLEGAL_MAJOR': Illegal major device number + * 'ERROR_IO_NO_SPACE': Device slot already allocated + * + ************************************************************************/ + INT32 FLASH_AMD_install( void ) ; + + + #endif /* #ifndef FLASH_AMD_API_H */ diff -cNr yamon-sde6/include/lan_au1x00_api.h yamon-devdrv/include/lan_au1x00_api.h *** yamon-sde6/include/lan_au1x00_api.h Thu Jan 1 09:00:00 1970 --- yamon-devdrv/include/lan_au1x00_api.h Mon Sep 26 17:35:55 2005 *************** *** 0 **** --- 1,57 ---- + #ifndef LAN_AU1X00_API_H + #define LAN_AU1X00_API_H + + /************************************************************************ + * + * LAN_AU1X00_api.h + * + * The 'LAN_AU1X00_api' module defines the specific public + * interface for the AU1X00 MAC device driver. + *************************************************************************/ + + + /************************************************************************ + * Include files + ************************************************************************/ + + #include "sysdefs.h" + + + /************************************************************************ + * Public functions + ************************************************************************/ + + /************************************************************************ + * + * LAN_AU1X00_install + * Description : + * ------------- + * + * Installs the LAN AM79C973 device drivers services in + * the IO system at the reserved device slot, found in the + * 'sysdev.h' file, which defines all major device numbers. + * + * Note: + * This service is the only public declared interface function; all + * provided device driver services are static declared, but this + * function installs the function pointers in the io-system to + * enable the provided public driver services. + * + * Parameters : + * ------------ + * + * - + * + * + * Return values : + * --------------- + * + * 'OK'(=0) + * 'ERROR_IO_ILLEGAL_MAJOR': Illegal major device number + * 'ERROR_IO_NO_SPACE': Device slot already allocated + * + ************************************************************************/ + INT32 LAN_AU1X00_install( void ); + + + #endif /* #ifndef LAN_AU1X00_API_H */ diff -cNr yamon-sde6/include/rtc_au1x00_api.h yamon-devdrv/include/rtc_au1x00_api.h *** yamon-sde6/include/rtc_au1x00_api.h Thu Jan 1 09:00:00 1970 --- yamon-devdrv/include/rtc_au1x00_api.h Wed Jul 20 18:05:52 2005 *************** *** 0 **** --- 1,202 ---- + + /************************************************************************ + * + * RTC_api.h + * + * The 'RTC' module implements a device driver + * for MC146818A/DS1685/DS1687 compatible RTCs. + * + * 1) init serial device: configure and initialize RTC driver + * 2) open serial device: not used + * 3) close serial device: not used + * 4) read serial device: get RTC + * 5) write serial device: set RTC + * 6) ctrl serial device: not used + * + * + * ###################################################################### + * + * Copyright (c) 1999-2000 MIPS Technologies, Inc. All rights reserved. + * + * Unpublished rights reserved under the Copyright Laws of the United States of + * America. + * + * This document contains information that is proprietary to MIPS Technologies, + * Inc. ("MIPS Technologies"). Any copying, modifying or use of this information + * (in whole or in part) which is not expressly permitted in writing by MIPS + * Technologies or a contractually-authorized third party is strictly + * prohibited. At a minimum, this information is protected under unfair + * competition laws and the expression of the information contained herein is + * protected under federal copyright laws. Violations thereof may result in + * criminal penalties and fines. + * MIPS Technologies or any contractually-authorized third party reserves the + * right to change the information contained in this document to improve + * function, design or otherwise. MIPS Technologies does not assume any + * liability arising out of the application or use of this information. Any + * license under patent rights or any other intellectual property rights owned + * by MIPS Technologies or third parties shall be conveyed by MIPS Technologies + * or any contractually-authorized third party in a separate license agreement + * between the parties. + * The information contained in this document constitutes one or more of the + * following: commercial computer software, commercial computer software + * documentation or other commercial items. If the user of this information, or + * any related documentation of any kind, including related technical data or + * manuals, is an agency, department, or other entity of the United States + * government ("Government"), the use, duplication, reproduction, release, + * modification, disclosure, or transfer of this information, or any related + * documentation of any kind, is restricted in accordance with Federal + * Acquisition Regulation 12.212 for civilian agencies and Defense Federal + * Acquisition Regulation Supplement 227.7202 for military agencies. The use of + * this information by the Government is further restricted in accordance with + * the terms of the license agreement(s) and/or applicable contract terms and + * conditions covering this information from MIPS Technologies or any + * contractually-authorized third party. + * + ************************************************************************/ + + #ifndef RTC_AU1X00_API_H + #define RTC_AU1X00_API_H + + /************************************************************************ + * Include files + ************************************************************************/ + + #include + #include + + /************************************************************************ + * Definitions + *************************************************************************/ + + /************************************************************************ + * RTC device driver, ERROR completion codes + *************************************************************************/ + typedef enum RTC_error_ids + { + ERROR_RTC_NO_FRAME /* No receive frame present */ + = ERROR_RTC, + ERROR_RTC_COMM_ERROR, /* Communication error detected */ + + /******* ADD NEW IO ERROR TAGS JUST BEFORE THIS LINE ONLY *******/ + + } t_RTC_error_ids; + + + /************************************************************************ + * Parameter definitions + *************************************************************************/ + + /* RTC value */ + typedef struct RTC_calendar + { + UINT16 year; + UINT16 month; + UINT16 dayofmonth; + UINT16 dayofweek; + UINT16 hour; + UINT16 minute; + UINT16 second; + } + t_RTC_calendar; + + + /************************************************************************ + * RTC device driver services, called by IO subsystem + *************************************************************************/ + + + /************************************************************************ + * + * NAME: 'init' + * + * Description : + * ------------- + * This service initializes the RTC driver. + * + * Return values : + * --------------- + * 'OK' = 0x00 + * + ************************************************************************/ + typedef INT32 (*t_RTC_init_service)( + UINT32 major, /* IN: major device number */ + UINT32 minor, /* not used */ + void *p_param ) ; /* not used */ + + + /************************************************************************ + * + * NAME: 'read' + * + * Description : + * ------------- + * This service reads the current value of the Real Time Clock. + * + * Return values : + * --------------- + * 'OK' = 0x00 current RTC-value read into user variable + * + ************************************************************************/ + typedef INT32 (*t_RTC_read_service)( + UINT32 major, /* IN: major device number */ + UINT32 minor, /* IN: minor device number */ + t_RTC_calendar *p_param ) ; /* INOUT: current RTC value */ + + + /************************************************************************ + * + * NAME: 'write' + * + * Description : + * ------------- + * This service sets the current value of the Real Time Clock. + * + * Return values : + * --------------- + * 'OK' = 0x00 RTC value has been set successfully + * + ************************************************************************/ + typedef INT32 (*t_RTC_write_service)( + UINT32 major, /* IN: major device number */ + UINT32 minor, /* IN: minor device number */ + t_RTC_calendar *p_param ) ; /* OUT: calendar value to set */ + + + /************************************************************************ + * Public functions + ************************************************************************/ + + + /************************************************************************ + * + * RTC_install + * Description : + * ------------- + * + * Installs the RTC device drivers services in the IO system + * at the reserved device slot, found in the 'sys_dev.h' file, + * which defines all major device numbers. + * + * Note: + * This service is the only public declared interface function; all + * provided device driver services are static declared, but this + * function installs the function pointers in the io-system to + * enable the provided public driver services. + * + * Parameters : + * ------------ + * + * None + * + * Return values : + * --------------- + * + * 'OK'(=0) + * 'ERROR_IO_ILLEGAL_MAJOR': Illegal major device number + * 'ERROR_IO_NO_SPACE': Device slot already allocated + * + ************************************************************************/ + INT32 + RTC_install( void ); + + #endif /* #ifndef RTC_AU1X00_API_H */ diff -cNr yamon-sde6/include/serial_api.h yamon-devdrv/include/serial_api.h *** yamon-sde6/include/serial_api.h Wed Mar 24 01:50:28 2004 --- yamon-devdrv/include/serial_api.h Wed Sep 21 14:53:03 2005 *************** *** 191,196 **** --- 191,201 ---- #define SERIAL_MINOR_TI16550_UART0 0 /* TI16550 UART subdev 0 */ #define SERIAL_MINOR_TI16550_UART1 1 /* TI16550 UART subdev 1 */ + #define SERIAL_MAX_AU1X00_DEVICES 3 /* max num AU1X00 async UARTs supported */ + #define SERIAL_MINOR_AU1X00_UART0 0 + #define SERIAL_MINOR_AU1X00_UART1 1 + #define SERIAL_MINOR_AU1X00_UART3 2 + /* Only one SAA9730 device */ #define SERIAL_MINOR_SAA9730_UART 0 /* SAA9730 UART */ diff -cNr yamon-sde6/include/serial_au1x00_api.h yamon-devdrv/include/serial_au1x00_api.h *** yamon-sde6/include/serial_au1x00_api.h Thu Jan 1 09:00:00 1970 --- yamon-devdrv/include/serial_au1x00_api.h Thu Sep 22 14:15:57 2005 *************** *** 0 **** --- 1,148 ---- + + /************************************************************************ + * + * SERIAL_AU1X00_api.h + * + * The 'SERIAL_AU1X00_api' module defines the specific public + * interface for the AU1X00 serial device driver. The + * generic serial device driver interface is defined in the + * 'serial_api' module, which is supported by this driver. + * + * The specific public interface comprise: + * + * 1) SERIAL_AU1X00_install: installs the 'serial' device driver + * services into the 'io' system. + * + * + * ###################################################################### + * + * This program is largely copies by the SERIAL_AU1X00 source files. + * + * Copyright 2005 Device Drivers Limited. + * Author: kawamoto@devdrv.co.jp + * + ************************************************************************/ + + #ifndef SERIAL_AU1X00_API_H + #define SERIAL_AU1X00_API_H + + /************************************************************************ + * Include files + ************************************************************************/ + + #include + #include + + + /************************************************************************ + * Definitions + *************************************************************************/ + + /* IER mask */ + #define SERIAL_IER_RCVEN 0x01 /* receive interrupt enable */ + + /* FCR control */ + #define SERIAL_FCR_ENABLE 0x01 /* enable FIFO's */ + #define SERIAL_FCR_RCVR_RESET 0x02 /* reset receiver FIFO */ + #define SERIAL_FCR_TXMT_RESET 0x04 /* reset transmit FIFO */ + #define SERIAL_FCR_RCVFIFO_1 0x00 /* receive FIFO threshold 1 */ + #define SERIAL_FCR_RCVFIFO_4 0x40 /* receive FIFO threshold 4 */ + #define SERIAL_FCR_RCVFIFO_8 0x80 /* receive FIFO threshold 8 */ + #define SERIAL_FCR_RCVFIFO_14 0xc0 /* receive FIFO threshold 14 */ + + /* LCR control */ + #define SERIAL_LCR_DATA5 0x00 /* 5-bit character */ + #define SERIAL_LCR_DATA6 0x01 /* 6-bit character */ + #define SERIAL_LCR_DATA7 0x02 /* 7-bit character */ + #define SERIAL_LCR_DATA8 0x03 /* 8-bit character */ + #define SERIAL_LCR_DATA_MSK 0x03 /* MASK for data field */ + + #define SERIAL_LCR_STOP1 0x00 /* 1 stop bit */ + #define SERIAL_LCR_STOP15 0x04 /* 1.5 stop bit, if data is 5-bit */ + #define SERIAL_LCR_STOP2 0x04 /* 2 stop bit */ + #define SERIAL_LCR_STOP_MSK 0x04 /* MASK for stop bit field */ + + #define SERIAL_LCR_PARITYNONE 0x00 /* No parity */ + #define SERIAL_LCR_PARITYODD 0x08 /* Odd parity */ + #define SERIAL_LCR_PARITYEVEN 0x18 /* Even parity */ + #define SERIAL_LCR_PARITYMARK 0x28 /* Mark parity */ + #define SERIAL_LCR_PARITYSPACE 0x38 /* Space parity */ + #define SERIAL_LCR_PARITY_MASK 0x38 /* MASK for parity field */ + + #define SERIAL_LCR_BREAK 0x40 /* request to send a 'break' */ + #define SERIAL_LCR_DLAB 0x80 /* enable divisor latch registers */ + + /* MCR control */ + #define SERIAL_MCR_DTR 0x01 /* Data Terminal Ready */ + #define SERIAL_MCR_RTS 0x02 /* Request To Send */ + #define SERIAL_MCR_OUT1 0x04 /* General purpose output */ + #define SERIAL_MCR_OUT2 0x08 /* General purpose output */ + + #define SERIAL_MCR_LOOP 0x10 /* Local loop back */ + #define SERIAL_MCR_AFE 0x20 /* Auto-flow control enable */ + + /* LSR status */ + #define SERIAL_LSR_DR 0x01 /* Character ready */ + #define SERIAL_LSR_OE 0x02 /* RX-ERROR: Overrun */ + #define SERIAL_LSR_PE 0x04 /* RX-ERROR: Parity */ + #define SERIAL_LSR_FE 0x08 /* RX-ERROR: Framing (stop bit)*/ + #define SERIAL_LSR_BI 0x10 /* 'BREAK' detected */ + #define SERIAL_LSR_THRE 0x20 /* Transmit Holding empty */ + #define SERIAL_LSR_TEMT 0x40 /* Transmitter empty (IDLE) */ + #define SERIAL_LSR_FIFOERR 0x80 /* RX-ERROR: FIFO */ + + + /* MSR status */ + #define SERIAL_MSR_DCTS 0x01 /* Delta clear to send */ + #define SERIAL_MSR_DDSR 0x02 /* Delta data set ready */ + #define SERIAL_MSR_TERI 0x04 /* Trailing edge ring ind. */ + #define SERIAL_MSR_DDCD 0x08 /* Delta data carrier detect */ + #define SERIAL_MSR_CTS 0x10 /* Clear to send */ + #define SERIAL_MSR_DSR 0x20 /* Data Set Ready */ + #define SERIAL_MSR_RI 0x40 /* Ring Indicator */ + #define SERIAL_MSR_DCD 0x80 /* Data carrier detect */ + + /* UBC UART Block Control */ + #define SERIAL_UBC_ME 0x02 /* Modem Enable */ + #define SERIAL_UBC_CE 0x01 /* Clock Enable */ + + + /************************************************************************ + * Public functions + ************************************************************************/ + + /************************************************************************ + * + * SERIAL_AU1X00_install + * Description : + * ------------- + * + * Installs the serial AU1X00 device drivers services in + * the IO system at the reserved device slot, found in the + * 'sys_dev.h' file, which defines all major device numbers. + * + * Note: + * This service is the only public declared interface function; all + * provided device driver services are static declared, but this + * function installs the function pointers in the io-system to + * enable the provided public driver services. + * + * Parameters : + * ------------ + * + * - + * + * + * Return values : + * --------------- + * + * 'OK'(=0) + * 'ERROR_IO_ILLEGAL_MAJOR': Illegal major device number + * 'ERROR_IO_NO_SPACE': Device slot already allocated + * + ************************************************************************/ + INT32 SERIAL_AU1X00_install( void ); + + + + #endif /* #ifndef SERIAL_AU1X00_API_H */ diff -cNr yamon-sde6/include/serial_au1x00_api.h_old yamon-devdrv/include/serial_au1x00_api.h_old *** yamon-sde6/include/serial_au1x00_api.h_old Thu Jan 1 09:00:00 1970 --- yamon-devdrv/include/serial_au1x00_api.h_old Wed Jul 20 17:36:37 2005 *************** *** 0 **** --- 1,54 ---- + + #ifndef SERIAL_AU1X00_API_H + #define SERIAL_AU1X00_API_H + + /************************************************************************ + * Include files + ************************************************************************/ + + #include + + + /************************************************************************ + * Definitions + *************************************************************************/ + + /************************************************************************ + * Public functions + ************************************************************************/ + + /************************************************************************ + * + * SERIAL_AU1X00_install + * Description : + * ------------- + * + * Installs the serial device drivers services in + * the IO system at the reserved device slot, found in the + * 'sys_dev.h' file, which defines all major device numbers. + * + * Note: + * This service is the only public declared interface function; all + * provided device driver services are static declared, but this + * function installs the function pointers in the io-system to + * enable the provided public driver services. + * + * Parameters : + * ------------ + * + * - + * + * + * Return values : + * --------------- + * + * 'OK'(=0) + * 'ERROR_IO_ILLEGAL_MAJOR': Illegal major device number + * 'ERROR_IO_NO_SPACE': Device slot already allocated + * + ************************************************************************/ + INT32 SERIAL_AU1X00_install( void ); + + + + #endif /* #ifndef SERIAL_AU1X00_API_H */ diff -cNr yamon-sde6/include/sys_api.h yamon-devdrv/include/sys_api.h *** yamon-sde6/include/sys_api.h Wed Mar 24 01:50:29 2004 --- yamon-devdrv/include/sys_api.h Wed Jul 20 13:24:45 2005 *************** *** 100,113 **** --- 100,125 ---- #endif /* Default baudrates for serial ports */ + #ifdef _ARCH_DEVDRV_EKIT1100 + #define DEFAULT_BAUDRATE SERIAL_BAUDRATE_115200_BPS + #define DEFAULT_DATABITS SERIAL_DATABITS_8 + #define DEFAULT_PARITY SERIAL_PARITY_NONE + #define DEFAULT_STOPBITS SERIAL_STOPBITS_10 + #define DEFAULT_FLOWCTRL SERIAL_FLOWCTRL_NONE + #else #define DEFAULT_BAUDRATE SERIAL_BAUDRATE_38400_BPS #define DEFAULT_DATABITS SERIAL_DATABITS_8 #define DEFAULT_PARITY SERIAL_PARITY_NONE #define DEFAULT_STOPBITS SERIAL_STOPBITS_10 #define DEFAULT_FLOWCTRL SERIAL_FLOWCTRL_HARDWARE + #endif /* #ifdef _ARCH_DEVDRV_EKIT1100 */ /* Default env. variable for serial port settings */ + #ifdef _ARCH_DEVDRV_EKIT1100 + #define DEFAULT_SERIAL_ENV "115200,n,8,1,none" + #else #define DEFAULT_SERIAL_ENV "38400,n,8,1,hw" + #endif /* #ifdef _ARCH_DEVDRV_EKIT1100 */ /* Board Serial number type */ diff -cNr yamon-sde6/include/sysdefs.h yamon-devdrv/include/sysdefs.h *** yamon-sde6/include/sysdefs.h Wed Mar 24 01:50:29 2004 --- yamon-devdrv/include/sysdefs.h Wed Jul 20 13:19:03 2005 *************** *** 445,456 **** --- 445,466 ---- #define PORT_TTY0 0 #define PORT_TTY1 1 #define PORT_NET 2 + #ifdef _ARCH_DEVDRV_EKIT1100 + #define DEFAULT_PORT PORT_TTY1 + #define DEBUG_PORT PORT_TTY1 + #define DEFAULT_GDB_PORT PORT_TTY0 + #else #define DEFAULT_PORT PORT_TTY0 #define DEBUG_PORT PORT_TTY0 #define DEFAULT_GDB_PORT PORT_TTY1 + #endif /* #ifdef _ARCH_DEVDRV_EKIT1100 */ /* Env. variable for default serial port used for load */ + #ifdef _ARCH_DEVDRV_EKIT1100 + #define DEFAULT_BOOTPORT_ENV "tty1" + #else #define DEFAULT_BOOTPORT_ENV "tty0" + #endif /* #ifdef _ARCH_DEVDRV_EKIT1100 */ /* Control characters */ #define CTRL_A ('A'-0x40) diff -cNr yamon-sde6/include/sysdev.h yamon-devdrv/include/sysdev.h *** yamon-sde6/include/sysdev.h Wed Mar 24 01:50:29 2004 --- yamon-devdrv/include/sysdev.h Mon Sep 26 10:25:36 2005 *************** *** 83,86 **** --- 83,88 ---- #define SYS_MAJOR_FLASH_STRATA 7 /* FLASH STRATA driver */ #define SYS_MAJOR_LAN_AM79C973 8 /* Ethernet driver: AM79C973 */ #define SYS_MAJOR_IDE 9 /* IDE driver */ + #define SYS_MAJOR_SERIAL_AU1X00 10 /* Serial driver: AU1X00 */ + #define SYS_MAJOR_LAN_AU1X00 11 /* Ethernet driver: AU1X00 */ #endif /* #ifndef SYSDEV_H */ diff -cNr yamon-sde6/shell/sample.c yamon-devdrv/shell/sample.c *** yamon-sde6/shell/sample.c Thu Jan 1 09:00:00 1970 --- yamon-devdrv/shell/sample.c Fri Aug 5 19:23:10 2005 *************** *** 0 **** --- 1,75 ---- + + /************************************************************************ + * Include files + ************************************************************************/ + + #include + #include + #include + #include + #include + + /************************************************************************ + * Definitions + ************************************************************************/ + + /************************************************************************ + * Public variables + ************************************************************************/ + + /************************************************************************ + * Static variables + ************************************************************************/ + + /************************************************************************ + * Static function prototypes + ************************************************************************/ + + /************************************************************************ + * Implementation : Static functions + ************************************************************************/ + + /************************************************************************ + * sample + ************************************************************************/ + static MON_FUNC(sample) + { + int i; + + printf("argc = %d\n", argc); + + if( argc > 1 ) + { + for(i = 0; i < argc; i++) + printf("argv[%d] = %s\n", i, argv[i]); + return OK; + } + else + { + return SHELL_ERROR_SYNTAX; + } + } + + + /* Command definition for help */ + static t_cmd cmd_def = + { + "sample", + sample, + "sample ", + "sample command.", + NULL, + 0, + FALSE + }; + + + /************************************************************************ + * Implementation : Public functions + ************************************************************************/ + + t_cmd * + shell_sample_init( void ) + { + return &cmd_def; + }